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Observer mustafaghanim
Observer
602 Views
Registered: ‎06-19-2019

HDMI output constraints of ZCU104, how to connect with AXI Stream Video Out

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I am trying to implement a Test Pattern Generator application with Microblaze in the target device ZCU104. I output my video data through AXI4-Stram to Video Out IP and I tried to understand HDMI Tx outputs for this device. Writing xdc file for theses outputs seems more complciated than I thought, how should I connect the vid_data [23:0] output to observe my pattern at HDMI output?


The general  constraints file for ZCU102 which is very similar to ZCU104 is uploaded. 

Edit: The Block Design of my project is added after including the HDMI TX Subsystem and AXI IIC as well.

 

 

 

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Moderator
Moderator
498 Views
Registered: ‎11-09-2015

Re: HDMI output constraints of ZCU104, how to connect with AXI Stream Video Out

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HI @mustafaghanim 

Please read PG235 chapter 5 for this. The example design build the BD and is not under petalinux...


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**

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Moderator
Moderator
549 Views
Registered: ‎10-04-2017

Re: HDMI output constraints of ZCU104, how to connect with AXI Stream Video Out

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Hi @mustafaghanim,

 

I am a little confused on what you are trying to accomplish. Are you trying to debug the output of the TPG? Are you trying to debug the output of the bridge core (AXI4-Stram to Video Out IP)? Are you trying to debug the output of the HDMI TX core?

 

If you are debugging the TPG or bridge core, I would suggest debugging these internally using ILAs. I am not sure that outputting these from the FPGA to the fabric is feasible due to finding enough available IO pins. (I have not double checked)

 

If you are debugging the HDMI TX core, I would suggest using a monitor/HDMI Analyzer/loopback into the FPGA and debug using an HDMI RX.

 

If I have not understood your question correctly, please add more information to help.

 

 

 

 

 

Don't forget to reply, kudo, and accept as solution.

Xilinx Video Design Hub
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Moderator
Moderator
523 Views
Registered: ‎11-09-2015

Re: HDMI output constraints of ZCU104, how to connect with AXI Stream Video Out

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HI @mustafaghanim 

From my understanding you are trying to use the AXI4-Stream to Video Out to connect on the HDMI connector of the ZCU104?

If this is correct, this is not gonna work. The HDMI corrector is connected to the GTs of the device. Thus you would need to use the Video PHY and HDMI TX Subsystem. Note that you are required to buy a license in order to use the HMDI TX subsystem but you can generate an evaluation license for free if you need to evaluate it (will have a timeout in the HW after few hours).

Regards


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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Observer mustafaghanim
Observer
517 Views
Registered: ‎06-19-2019

Re: HDMI output constraints of ZCU104, how to connect with AXI Stream Video Out

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I am trying to observe the TPG output ( video pattern) through AXI-4 AXI-4 Stream to Video Out to my HDMI supporting screeen. However, this seems not simple as I had thought. I am planning to use Vivado SDK example of "Tx Only" that uses communication with IIC. I have added HDMI Tx Subsystem for this purpose. However, I am currently stuck at the point where I should connect my HDMI outputs at the Block Design to the real hardware pins in ZCU104 FPGA pins.
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Moderator
Moderator
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Registered: ‎11-09-2015

Re: HDMI output constraints of ZCU104, how to connect with AXI Stream Video Out

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Hi @mustafaghanim 

Did you try with the ZCU104 TX only (both Vivado example design and HDMI TX only application)?

You might want to refer to PG235 chapter 5 for this


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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Observer mustafaghanim
Observer
509 Views
Registered: ‎06-19-2019

Re: HDMI output constraints of ZCU104, how to connect with AXI Stream Video Out

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I think we have got the licence for HDMI IPs. I have included my block design with the HDMI Tx Subsystem. For a simple and constant frequency of 148.5 MHz which is synthized in my Clock Wizard, what method should I follow to connect HDMI Tx and Video PHY with my ZCU104 HDMI output unit which consists of the following ports:

Sketch.png

Moreover, I could not find really useful tutorials related to ZCU boards for Block Design with Vivado and HDMI . I cannot use PetaLinux at the cuurent moment. 

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Moderator
Moderator
499 Views
Registered: ‎11-09-2015

Re: HDMI output constraints of ZCU104, how to connect with AXI Stream Video Out

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HI @mustafaghanim 

Please read PG235 chapter 5 for this. The example design build the BD and is not under petalinux...


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**

View solution in original post

Observer mustafaghanim
Observer
495 Views
Registered: ‎06-19-2019

Re: HDMI output constraints of ZCU104, how to connect with AXI Stream Video Out

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Thank you so much. This could be really helpful to learn more about HDMI in Block Design
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