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Adventurer
Adventurer
430 Views
Registered: ‎10-07-2016

HDMI2.0 Tx subsystem reference design with native Interface available ?

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Dear community memebers,

does anybody know a reference design, where the HDMI2.0 Tx subsystem is used by implementing the native interface, instead of the AXI-streaming interface?

best regards

Steffen

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1 Solution

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Adventurer
Adventurer
197 Views
Registered: ‎10-07-2016

Re: HDMI2.0 Tx subsystem reference design with native Interface available ?

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Hello xud,

the question is how the VTC achieves synchronization. Since it does not tune the pixel clock, I assume it does line adding in the vblank phase. This is not what we want to do, since most displays does not work with line adding...

That was the reason in the past why we build our own timing generator which allows us SOF synchronization between any input timing, and any output timing.

Do you know what I mean?

Kind regards

Steffen

 

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14 Replies
Xilinx Employee
Xilinx Employee
373 Views
Registered: ‎08-02-2007

Re: HDMI2.0 Tx subsystem reference design with native Interface available ?

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@stgateizo

There is no plan to provide  native interface example design.

The difference between native and AXI4 video interface is there is a video bridge (AXI4 Stream to Video Out) IP inside HDMI TX Subsystem IP, when using AXI4 Video Interface.

 AXI.JPG

You can use example design, and then use native interface HDMI TX IP to replace the AXI4 Stream interface HDMI TX, and then add VTC and AXI4 Stream to Video Out IP manually, so you should have more control on native interface.

Adventurer
Adventurer
340 Views
Registered: ‎10-07-2016

Re: HDMI2.0 Tx subsystem reference design with native Interface available ?

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Hello xud,

looks like there is an example design available, or from where have you copied this picture of the block diagram?

Kind regards

Steffen

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Xilinx Employee
Xilinx Employee
331 Views
Registered: ‎08-02-2007

Re: HDMI2.0 Tx subsystem reference design with native Interface available ?

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@stgateizo

The screenshot is from PG235, it shows the internal structure when video interface is AXI4 Stream.

The example design generation steps are documented in chapter 5 of PG235. After you generate it, -> remove HDMI TX-> add HDMI TX with native interface, refer to the screenshot in my last reply, add VTC and Video out IP manually

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Adventurer
Adventurer
322 Views
Registered: ‎10-07-2016

Re: HDMI2.0 Tx subsystem reference design with native Interface available ?

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Hello xud,

The interface "video_in" on the "v_hdmi_tx" IP-core is a native interface. The IP-Core "AXI-Stream To Video Out" converts the AXI-Streaming signals to the native Interface (Vs, Hs, DE, etc.). This is exactly the design I'm looking for.

Why can't you sent me the design described in PG235. Is it a secret ?

Kind regards

Steffen

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Xilinx Employee
Xilinx Employee
315 Views
Registered: ‎08-02-2007

Re: HDMI2.0 Tx subsystem reference design with native Interface available ?

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@stgateizo

I only modified it in old version of vivado, there was a lot changes in HDMI IP since then.

So it's better to follow the steps in Chapter 5 of PG235, and modify it. If you have problem to make it work, please attach the design, I will have a look.

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Adventurer
Adventurer
307 Views
Registered: ‎10-07-2016

Re: HDMI2.0 Tx subsystem reference design with native Interface available ?

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Hello xud,

when I understand you right, I should do the following steps:

  1. Create an HDMI Tx Subsystem example design by selecting "AXI-Streaming Interface", instead of "Native Interface".
  2. Reconfigure afterwards HDMI Tx Subsystem in example design, by selecting "Native Interface"
  3. Instantiate "Video Timing Controller" and "AXIS To Video Out" IP-Core.

If so this brings me to the following questions:

  1. Your block diagram shows only the interface connections, but not the clocks, resets, and other signals which needs to be connected anyhow.
      How do I have to connect all the stuff?
  2. Provided, I have overcome point 1) and implemented the design in vivado, what do I have to do in SDK?
    I assume I can no longer use the API functions from the HDMI Tx Subsystem, since some functions are no longer implemented in the HDMI Tx Subsystem?

Kind regards

Steffen

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Xilinx Employee
Xilinx Employee
284 Views
Registered: ‎08-02-2007

Re: HDMI2.0 Tx subsystem reference design with native Interface available ?

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@stgateizo

Yes, the mentioned steps are correct.

1) Please give it a try, if you have questions related to interface connection. I will follow up with this offline.

2) Even though you generate HDMI TX with native interface, you can still use HDMI TX SS driver.

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Adventurer
Adventurer
265 Views
Registered: ‎10-07-2016

Re: HDMI2.0 Tx subsystem reference design with native Interface available ?

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Hello xud,

please see my comments below:

1) Please give it a try, if you have questions related to interface connection. I will follow up with this offline
Okay

2) Even though you generate HDMI TX with native interface, you can still use HDMI TX SS driver.
So what do I have to do when I want to adjust the output timing? Do I have to call the same functions as in the HDMI Tx Subsystem Xilinx example design (with AXI-Streaming Interface)?

And from where do I get the code to program the timing controller which is placed outside of the HDMI Tx Subsystem?

Kind regards
Steffen

 

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Scholar watari
Scholar
242 Views
Registered: ‎06-16-2013

Re: HDMI2.0 Tx subsystem reference design with native Interface available ?

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Adventurer
Adventurer
230 Views
Registered: ‎10-07-2016

Re: HDMI2.0 Tx subsystem reference design with native Interface available ?

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Hello xud, watari,

Uuuh, this will result im cumbersome reverse engineering actions. This has not really soemthing to do with ultra fast design methodology!
Without any example design, it takes me probably several weeks to get the stuff (maybe) running.

The problem is that I will mostlikely not get time to do it that way, and furthermore it is unsafe.

I will try to find another way to overcome our issue.

Thanks & best regards

Steffen

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Xilinx Employee
Xilinx Employee
223 Views
Registered: ‎08-02-2007

Re: HDMI2.0 Tx subsystem reference design with native Interface available ?

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@stgateizo

Steffen,

You don't need to change anything in HDMI driver, the API should handle this. It checks whether VTC is included or not, and then handle it accordingly.

XV_HdmiTxSs_VtcSetup in xv_hdmitxss.c is used to setup VTC.

Please have a close look at API XV_HdmiTxSs_StreamUpCallback, it checks if VTC is inside HDMI TX Subsystem or not. if not, it doesn't setup the VTC parameter, so you need to set it up manually.

if (HdmiTxSsPtr->VtcPtr) {

/* Setup VTC */ 

XV_HdmiTxSs_VtcSetup(HdmiTxSsPtr);

}

 

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Adventurer
Adventurer
216 Views
Registered: ‎10-07-2016

Re: HDMI2.0 Tx subsystem reference design with native Interface available ?

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Hello Xud,

okay, I understand what you mean, and how it works.

Xud, maybe you can help me with a related question. My goal is actually to synchronize the output timing of the HDMI Tx Subsystem to a DVI input timing. With synchronization I mean Vsync (SOF) synchronous. From a previous project I can reuse a self-created video timing controller, which allows me to synchronize the output timing to an input timing, by using pixel-clock tuning which is done by an external PLL. In other words, the pixel-clock is tuned by a regualtion circuit in such a way, that both timings will run SOF synchronous. This self-developed timing controller is working very well in other projects, and now I'm looking for a way how I can integrate this video timing controller in a design where it should drive the native interface of the HDMI Tx Subsystem.

So my video timing controller, which is running with this tuned pixel clock has the same output signals as the VTC from Xilinx. From this point of view I do not see a connection problem. But how do I have to connect the tuned pixel clock to the HDMI Tx Subsystem?

When I look to the HDMI pass-through design, the received pixel-clock will be looped-though the FPGA and drives an external PLL (SI5324), which in turn drives the GT-RefClk of the HDMI Tx MGT Channels.

When I would connect the tuned pixel clock from my external PLL with the GT-RelClk input, do you think if this could work?

grafik.pngUse tuned pixel clock for HDMI Tx subsystem

Kind regards

Steffen

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Xilinx Employee
Xilinx Employee
202 Views
Registered: ‎08-02-2007

Re: HDMI2.0 Tx subsystem reference design with native Interface available ?

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@stgateizo

The output of HDMI TX is link data. In our design, we use AXI4-Stream to Video Out IP : https://www.xilinx.com/support/documentation/ip_documentation/v_axi4s_vid_out/v4_0/pg044_v_axis_vid_out.pdf

Sometimes we call it video bridge, as it converts the data between AXI4 Stream(driven by aclk) to Native video domain (driven by vid_io_out_clk).

This IP also synchronous the timing from Video AXI4 Stream data (with tuser) and the timing from VTC (sof). Internally there is a state machine used to align the tuser to the sof of VTC, Once they are synced, lock signal is asserted, then the native timing associated to video pixel data send to HDMI TX.

So timing synchronization is done before HDMI TX, not after.

In your case, you use native interface, the timing from VTC can be driven to HDMI TX, but can you show me how video data is generated before sending to HDMI TX?  I think probably you need to turn the clock, which is used to generate video data, make it align with the timing generated from  your VTC.

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Adventurer
Adventurer
198 Views
Registered: ‎10-07-2016

Re: HDMI2.0 Tx subsystem reference design with native Interface available ?

Jump to solution

Hello xud,

the question is how the VTC achieves synchronization. Since it does not tune the pixel clock, I assume it does line adding in the vblank phase. This is not what we want to do, since most displays does not work with line adding...

That was the reason in the past why we build our own timing generator which allows us SOF synchronization between any input timing, and any output timing.

Do you know what I mean?

Kind regards

Steffen

 

0 Kudos