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Registered: ‎05-24-2013

Hi, please help me with the black box error

Here is the error file

Version                                 Path
System Generator 13.4                   C:/Xilinx/13.4/ISE_DS/ISE/sysgen
Matlab (R2010a)              C:/Program Files/MATLAB/R2010a
ISE                                     C:/Xilinx/13.4/ISE_DS/ISE
Summary of Errors:
Error 0001: Undriven input port
     Block: 'rnsworeset/Black Box'

Error 0001:

Reported by:
  'rnsworeset/Black Box'

The input ports on this block must be driven by other Xilinx blocks

 connection of constant zero as reset input to black box through the GateWay in1 is giving error even i tried with the constant block which is available in xilinx blockset then also i am getting the same error.

the error report and model are attached.

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3 Replies
Xilinx Employee
Xilinx Employee
Registered: ‎08-02-2011

Re: Hi, please help me with the black box error

I think the clock probe is the problem.


This is not the proper way to drive a clock into a black box. Please read through the black box section of the sysgen user guide for details.
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Registered: ‎04-25-2013

Re: Hi, please help me with the black box error

Try using another port called ce and when ever u use clock check whether ce is one or not if clk and ce = 1 then the logic if used in pairs the m function generator will automatically detect the clock port u need not drive it externally.


Plz GO through it may help u


Black Box HDL requirements and Restrictions


An HDL component associated with a black box must adhere to the following System
Generator requirements and restrictions:
• The entity name must not collide with any other entity name in the design.
• Bi-directional ports are supported in HDL black boxes, however they will not be
displayed in the System Generator as ports; they only appear in the generated HDL
after netlisting.
• For Verilog black boxes, the module and port names must be lower case and must
follow standard VHDL naming conventions.
• Any port that is a clock or clock enable must be of type std_logic. (For Verilog black
boxes, ports must be of non-vector inputs, e.g., input clk.)
• Clock and clock enable ports in black box HDL should be expressed as follows: Clock
and clock enables must appear as pairs (i.e., for every clock, there is a corresponding
clock enable, and vice-versa). Although a black box may have more than one clock
port, a single clock source is used to drive each clock port. Only the clock enable rates
• Each clock name (respectively, clock enable name) must contain the substring clk, for
example my_clk_1 and my_ce_1.
• The name of a clock enable must be the same as that for the corresponding clock, but
with ce substituted for clk. For example, if the clock is named src_clk_1, then the
clock enable must be named src_ce_1.
• Falling-edge triggered output data cannot be used.

Thanks and Regards
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Registered: ‎11-21-2012

Re: Hi, please help me with the black box error

in the port description you should have clk and ce togther.

for example:

module a(clk,ce,in1,in2,out1,out2);

input wire clk,ce;


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