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Adventurer
Adventurer
361 Views
Registered: ‎05-18-2018

How do I configure AXI VDMA & AXI4-Video to Stream blocks to avoid skipped pixels?

I am trying to port a video controller module over to US+ from a working Zynq design in Vivado 2019.1. The older design used an 800x600 LCD screen; the new design uses a 1024x600 LCD screen.

I am getting video to appear on my screen, but the data being sent is interspersed with 0x00000000, like so:

data_waveforms.pngThe problem shown in this waveform is borne out on the screen by having one correctly displayed 0x00FF00FF pixel and one black 0x00000000 pixel.

A detail of my block diagram:

 

BD.png

Per the AXI VDMA guide advice, my synchronous VDMA has its ACLKs all tied to the same 150 MHz fabric clock. (However, the original working Zynq project had the s_axi_lite_aclk tied to a 75 MHz fabric clock and the m_axi*_mm2s_aclk signals tied to a separate150 MHz fabric clock; I've tried this configuration and it did work.)

I understand the FPGA side far better than the PS side code, but I am not toally convinced this isnt a PL-side IP configuration problem.

My IP configuration screens:

 

AXI4StoV_1.png

 

VDMA_config_1.png

 

VDMA_config_2.png

 

The video data is coming out of the VDMA block with the unwanted 0x00000000 pixels. Upstream of that, I'm having trouble tracing the problem.

Vivado video experts, are there any obvious configuration issues?

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1 Reply
Moderator
Moderator
250 Views
Registered: ‎11-09-2015

Re: How do I configure AXI VDMA & AXI4-Video to Stream blocks to avoid skipped pixels?

Hi @joelschad 

Can you configure the timing from the Static Video Timing Generator? Else this is what you are missing first.

You might want ot have a look at my Video Series for basics of Video Design. Specifically the following ones can be useful:

Video Beginner Series 16: Understanding Video Timing with the VTC IP

Video Series 19: Using the On-Board HDMI on ZC702 (Vivado design)

Video Series 20: Starting with SDK and configuring the ADV7511

Video Series 21: TPG Application on ZC702

Video Series 22: Supporting multiple video resolutions on ZC702 HDMI

Video Series 23: Generate a video output on Pynq-Z2 HDMI out

Video Series 24: Using the AXI VDMA in Triple Buffer Mode

Regards


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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