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Visitor msattine
Visitor
835 Views
Registered: ‎11-27-2018

How is calibration dealt in case of multiple MIPI receiver configuration where one is instantiated as master

Hi,

    I am facing an issue with multiple MIPI receiver configuration where one is instantiated as master and other three as slaves as shown in attached figure. The problem is that the data out of one of the slaves is skewed by 32 samples (Observation: x samples sampled out of master and two slaves whereas (x+32) samples sampled out of other slave in the same time. After a while this resulted in lane buffer full condition in this slave.

I am still trying to narrow down the issue and wanted to check if issue is around the way the MIPI receivers are configured.

The lane lengths from sources are different, which means that all four devices have different I/O delays, but they are synchronous at source side. I am thinking if the issue is to do with the way calibration is dealt in this configuration. Not much information provided in the IP product page.

Any help and suggestions in this regard is appreciated.

Regards,

Mohan.

 

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Xilinx Employee
Xilinx Employee
766 Views
Registered: ‎03-07-2018

Re: How is calibration dealt in case of multiple MIPI receiver configuration where one is instantiated as master

Hello @msattine

As per https://www.xilinx.com/support/answers/71374.html; When multiple D-PHY IPs are placed in the same bank, they need to be reset at the same time even if they are independent IP.

Can you please check on that? Also check  for more information.

Are you getting any critical warnings while implementing design? 

Regards,
Bhushan

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Visitor msattine
Visitor
758 Views
Registered: ‎11-27-2018

Re: How is calibration dealt in case of multiple MIPI receiver configuration where one is instantiated as master

Hi Bhushan,

        Thanks for the reply.

I checked on the rest. And as can be observed from the image in my initial post, rst_250M_n is connected to all the IP instances so I assume that takes care of resetting all MIPI DPHYs together.

I dont see any critical warning that fall related to IP instances.

Please let me know if you need more details.

Regards,

Mohan.

Xilinx Employee
Xilinx Employee
736 Views
Registered: ‎03-30-2016

Re: How is calibration dealt in case of multiple MIPI receiver configuration where one is instantiated as master

Hello Mohan @msattine

Unfortunately, the skewed data issue is an expected result.
( This will happen even if you are having exactly the same wire lenght for each MIPI channel on your board )

1. MIPI Master-IP and Slave-IP are sharing PLL and clock resources only.
2. Your four MIPI IP instances are working independently.
   Each IP does not know the state of other IP. Their video output data is not aligned.
For a work-around, you well need create a custom line-buffer to hold video-data from four IPs,
and aligned all the data before you can use it.


Regarding the buffer-full condition, to give your a debug direction I willl need more information.
1. Please provide XCI for your MIPI IP instances.
2. Please share all MIPI CSI-2 RX register dump.
3. Tell me the clock frequency of video_aclk ?
4. Is your video_out_tready fixed to "1" ?

Thanks and regards
Leo

Visitor msattine
Visitor
723 Views
Registered: ‎11-27-2018

Re: How is calibration dealt in case of multiple MIPI receiver configuration where one is instantiated as master

Hi Leo,

          Whatever I mentioned in my initial post is just the initial skew in data. But when I run it for long time, I observed a very large skew in data samples from the four sensors. This actually means that some samples are missing from some sensors in long run which is not expected.

In the actual implementation we have a axis combiner where the streams from all the four IP instances are combined to a larger stream and connected to DMA. For debug purpose I disconnected the axis combiner and tied tready's of all instances to high and added counters to count number of tvalid's from all instances. This is done over a period of time and observed that the counts mismatch by a large difference. In this case it is observed that frame synchronization for VC0 is set, CRC error is set and SoT sync error is set.

I will share the XCI and register dump in some time.

Regards,

Mohan.

Xilinx Employee
Xilinx Employee
717 Views
Registered: ‎03-30-2016

Re: How is calibration dealt in case of multiple MIPI receiver configuration where one is instantiated as master

Mohan @msattine

Thanks for the additional information. This is not good.
Please share your XCI file. ( Need to check the IP version and configuration )
Are you using sensors with continuous clock-mode or non-continuous clock-mode ?

Thanks & regards
Leo

 

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Visitor msattine
Visitor
699 Views
Registered: ‎11-27-2018

Re: How is calibration dealt in case of multiple MIPI receiver configuration where one is instantiated as master

Hi Leo,

     Please find the attached xci files of the four instances and also the register content. Please note that it is not consistent across the runs. 

Another observation is that there is no data capture happening at all when the part is gaining temperature.

Sensors are operating in non-continuous clock mode.

Regards,

Mohan.

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Xilinx Employee
Xilinx Employee
693 Views
Registered: ‎03-30-2016

Re: How is calibration dealt in case of multiple MIPI receiver configuration where one is instantiated as master

Hello Mohan @msattine

You are using MIPI CSI-2 RX IP from 2017.4, it may not work with non-continous clock-mode.

Please see :
https://www.xilinx.com/support/answers/70581.html

If you want to try the patch, please download at
https://www.xilinx.com/support/answers/70530.html
But I do recommend to use IP from Vivado 2018.3.

Hope this helps.

Thanks & regards
Leo

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Visitor msattine
Visitor
643 Views
Registered: ‎11-27-2018

Re: How is calibration dealt in case of multiple MIPI receiver configuration where one is instantiated as master

Hi Leo,

  Thank you very much for the details.

Figured out that it is possible to configure sensor for continuous clock mode. Tried setting the sensors to this configuration. Definitely there is improvement over earlier runs, but it didnt solve it completely. The issue showed up after running for some time.

What is your suggestion? Should we try debug why it is not working with continuous mode set? Or should we migrate to vivado 2018.3?

Regards,

Mohan.

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Xilinx Employee
Xilinx Employee
527 Views
Registered: ‎03-30-2016

Re: How is calibration dealt in case of multiple MIPI receiver configuration where one is instantiated as master

Hello Mohan @msattineThank you for updating the status.

If this is a new design project and you have the time to upgrade design to 2018.3, using IP from 2018.3. is the best option. but Migrating to the latest 2018.3 might be time-consuming.
(Additionally, MIPI CSI-2 RX Subsystem has some video data I/F changes in 2018.3 for multi pixel output per-beat. So I do not want to bring you more confusion during design migration )

Since you are using IP from 2017.4, my recommendation is to use the following patch :
https://www.xilinx.com/support/answers/70581.html

Please share your register dump and ILA capture, if you still have an issue with 2017.4 + patch.


Thanks & regards
Leo

 

Moderator
Moderator
461 Views
Registered: ‎11-09-2015

Re: How is calibration dealt in case of multiple MIPI receiver configuration where one is instantiated as master

Hi @msattine,

Do you have any updates on this? Are you happy enough with @karnanl's replies?

If your question is answered or your issue is solved, please kindly mark the response which helped as solution (click on "Accept as solution" button below the reply)

If this is not solved/answered, please reply in the topic giving more information on your current status.

Thanks and Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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Visitor msattine
Visitor
415 Views
Registered: ‎11-27-2018

Re: How is calibration dealt in case of multiple MIPI receiver configuration where one is instantiated as master

Hi Leo,

I tried with the patch and the result is the same. The capture is not happening once the device ia gaining some temperature. Do you think migrating to new version is good or should we be looking at other possibilities?

Regards,

Mohan.

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Visitor msattine
Visitor
370 Views
Registered: ‎11-27-2018

Re: How is calibration dealt in case of multiple MIPI receiver configuration where one is instantiated as master

Hi Leo,

      Below is further description of the debug so far:

I checked data capture from individual sensor alone. The observation is the same for all the sensors and the data capture is not at all happening after some time when the device is gaining temperature. Looking at the register content both the line count in DPHY and packet count in CSI-2 are stuck to a value after the issue. And some times only packet count in CSI-2 is stuck to a value. Not sure if it is something to do withe the way MIPI PPI level signals are aligned.

We have another implementation which is for single sensor and this is on zynq 9eg board and we didnt face any issue there. Any suggestions for further debug is appreciated.

Regards,

Mohan.

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Xilinx Employee
Xilinx Employee
327 Views
Registered: ‎03-30-2016

Re: How is calibration dealt in case of multiple MIPI receiver configuration where one is instantiated as master

Hello Mohan @msattine

Thank you for the update.

>I checked data capture from individual sensor alone.
>The observation is the same for all the sensors and the data capture is not at all happening after some time when the device is gaining temperature.
>Looking at the register content both the line count in DPHY and packet count in CSI-2 are stuck to a value after the issue.
>And some times only packet count in CSI-2 is stuck to a value. Not sure if it is something to do withe the way MIPI PPI level signals are aligned.

Okay, could you please share your register dump for MIPI CSI-2 and MIPI D-PHY IP ?
I can double check them.


>We have another implementation which is for single sensor and this is on zynq 9eg board and we didnt face any issue there.
>Any suggestions for further debug is appreciated.


Are you using IP evaluation license ? You can check IP license status on the IP GUI.
If yes, then this is an expected behavior. You may intrested to check the following post.
https://forums.xilinx.com/t5/Video/mipi-csi-2-RX-operation-time-limit/m-p/923116
 

Thanks & regards
Leo

Moderator
Moderator
60 Views
Registered: ‎11-09-2015

Re: How is calibration dealt in case of multiple MIPI receiver configuration where one is instantiated as master

Hi @msattine,

Do you have any updates on this?

If your question is answered or your issue is solved, please kindly mark the response which helped as solution (click on "Accept as solution" button below the reply)

If this is not solved/answered, please reply in the topic giving more information on your current status.

Thanks and Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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Visitor msattine
Visitor
55 Views
Registered: ‎11-27-2018

Re: How is calibration dealt in case of multiple MIPI receiver configuration where one is instantiated as master

Hi,

    As I mentioned earlier, the issue is not resolved even after using conitnuous clock mode and using patch.

Please use the register content that I attached in my 10th Jan post as reg_data.txt.

The issue is seen once the fpga is gaining heat. What is the temperature range that the IP is expected to work? Given the data rate of 1000 Mbps per lane.

Regards,

Mohan.

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Xilinx Employee
Xilinx Employee
28 Views
Registered: ‎03-30-2016

Re: How is calibration dealt in case of multiple MIPI receiver configuration where one is instantiated as master

Hello Mohan @msattine

>The issue is seen once the fpga is gaining heat. What is the temperature range that the IP is expected to work?
>Given the data rate of 1000 Mbps per lane.

ZU+ MPSoC should operate at the following Junction temp:
TEMP_ZU+.png

Did you try IP from Vivado 2018.3 ? 
Older MIPI D-PHY IP did not enable internal termination. It may cause issue when signal margin is small. Please see:
https://www.xilinx.com/support/answers/71582.html 

Or you can also try to add the following setting on your XDC, if you cannot upgrade to 2018.3 

set_property DIFF_TERM_ADV TERM_100 [get_ports <clk_rxp/n>] 
set_property DIFF_TERM_ADV TERM_100 [get_ports <data_rxp[*]/n[*]>]

Thanks & regards
Leo

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