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Visitor aae65
Visitor
4,091 Views
Registered: ‎06-17-2013

IP Core Generator DDS compiler

Hi,

I am trying to use the DDS compiler to generate a sinusoid signal. However, i am getting errors after i try to generate the IP Core.

The only parameters i am specifying/changing are the output width (under hardware paramterss); i am setting it to 16 bits, and i am setting the phase angle increment value to 100001 (decimal 33) so that my output frequency will be almost 50khz, i am also unticking the phase-out as i won't need it. Also, i kept the phase qidth at its default value of 16 bits. After i click on generate i get the following errors:

 

ERROR:sim - Failed to generate 'sinusoidcore'. 
ERROR:sim - "C:/Users/student/Xilinx
   projects/sinusoid16/ipcore_dir/tmp/./_cg/_dbg/./dds_compiler_v4_0/sin_cos.vhd
   " line 228: Real operand is not supported in this context.
ERROR:sim -  Process will terminate. For technical support on this issue, please
   open a WebCase with this project attached at http://www.xilinx.com/support
ERROR:sim - Failed executing Tcl generator.
ERROR:sim - Failed to generate 'sinusoidcore'.  Failed executing Tcl generator.

 

I tried opening the .vhd file in the 2nd error but it seems to be encrypted (because it is intellectual property i guess).

Any thoughts on how to solve this? (i attached the .vhd file that the error pointed to)

Thank You,

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4 Replies
Xilinx Employee
Xilinx Employee
4,083 Views
Registered: ‎08-02-2011

Re: IP Core Generator DDS compiler

What version of the tools are you using? What device are you targeting?
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Visitor aae65
Visitor
4,079 Views
Registered: ‎06-17-2013

Re: IP Core Generator DDS compiler

I am using ISE 14.2 and targeting a Virtex 5 FX30T FPGA

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Xilinx Employee
Xilinx Employee
4,074 Views
Registered: ‎08-02-2011

Re: IP Core Generator DDS compiler

Unfortunately, this is a known issue for certain specific configurations of this version of the core.

Your options:
- Use another version of the core
- Generate the core in 13.4 and bring it forward.
- Use 15 bits instead of 16
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Visitor raghav.vlsi
Visitor
1,434 Views
Registered: ‎07-22-2015

Re: IP Core Generator DDS compiler

hi

 

we should have to change the phase input sto 15 

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