06-27-2013 04:57 AM
I am trying to use the DDS compiler to generate a sinusoid signal. However, i am getting errors after i try to generate the IP Core.
The only parameters i am specifying/changing are the output width (under hardware paramterss); i am setting it to 16 bits, and i am setting the phase angle increment value to 100001 (decimal 33) so that my output frequency will be almost 50khz, i am also unticking the phase-out as i won't need it. Also, i kept the phase qidth at its default value of 16 bits. After i click on generate i get the following errors:
ERROR:sim - Failed to generate 'sinusoidcore'.
ERROR:sim - "C:/Users/student/Xilinx
" line 228: Real operand is not supported in this context.
ERROR:sim - Process will terminate. For technical support on this issue, please
open a WebCase with this project attached at http://www.xilinx.com/support.
ERROR:sim - Failed executing Tcl generator.
ERROR:sim - Failed to generate 'sinusoidcore'. Failed executing Tcl generator.
I tried opening the .vhd file in the 2nd error but it seems to be encrypted (because it is intellectual property i guess).
Any thoughts on how to solve this? (i attached the .vhd file that the error pointed to)
06-28-2013 11:21 AM