12-14-2018 07:09 AM
Does anyone has a working implementation multiple GT in the same quad? I'm trying to follow the following example found on the pg290-v-smpte-uhdsdi-rx-ss.pdf document.
Not all I/Os are connected in this capture so I'm not sure how to do it. Moreover, let say I need 4 GTs in the same quad. do you configure the slave GT with 3 links?
12-17-2018 08:03 AM
It depends on your requirements. If you need to have 4 separate lanes, then you need to have 1 master UHD_SDI GT and 3 slaves. All the slaves needs to be connected using the same way with the master (for qpll lock).
Let me know if you have any issues with this.
12-17-2018 08:14 AM
12-17-2018 08:26 AM
I believe the cmp_gt_ctrl bus should be connected to the same input as the master.
The bit 0 and 1 of cmp_gt_sts is giving you the QPLL lock status so this is what you need to connect to the slave.
The version 2018.3 of the PG290 is giving a better detail of each of the bit of both the control and status signal.
12-17-2018 08:49 AM
Do you have a working example?
For now we are using 2018.2. The GT master is one SDI link. The slave is configured is configured with 3 SDI links.
I don't find the document very clear.
12-17-2018 09:03 AM
I do not have a working example but I had customer successful so I know it can work.
Are you able to generate a bitsream or do you get any error in the earlier steps?
12-17-2018 09:05 AM
I was able to generate the bitfile. But it seems the rxoutclk/txoutclk for the slaves are not generated...
12-17-2018 09:14 AM
Could you try to add an ILA to the cmp_gt_sts of at least one slave? This should give information on whether the PLLs are locked.
01-04-2019 02:48 AM
Bonne Année 2019!
What is you current status on this? Did you make any progress?
01-04-2019 05:08 AM
Thanks for following this up. Bonne année 2019!
Yes we've made progress but we still have some tests to perform next week.
We were able to have a passthrough working on at least one GTH of the quad but not all of them.
I still need to investigate.
I'll keep you posted.
01-07-2019 09:14 AM
I'm facing the same problem as you were previously, where rxoutclk and txoutclk don't seem to be generated properly, and since you seem to have figured it out, could you please share the solution as it might be the same issue in my design.
Thanks in advance,
01-10-2019 06:30 AM
01-10-2019 06:32 AM
You should create a new topic for your issue. Not every design or issue will be the same.
Share screenshot of how you have done it.
01-10-2019 06:39 AM
Will do but later as our debugging is not finished. We're migrating to 2018.3.
By the way, @florentw, in the IPI, can we use implement only one instance of the IP where we use 4 GTs?
For now, I do use 2 instances:
01-10-2019 06:47 AM
It depends on your system. If the 4 lanes are fully independent, I recommend to use 4 UHD SDI GT
01-10-2019 06:59 AM - edited 01-10-2019 07:13 AM
Well they're located in the same quad, each of them receiving independant SDI video and able to send SDI video in passthrough.
All four GTH, in the quad, share the same QPLL0 (Rx) and QPLL1 (Tx). We use an external PLL for jitter filtering.