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Explorer
Explorer
525 Views
Registered: ‎03-17-2011

Implementation multiple GT in the same quad (SMPTE SDI)

Hello,

Does anyone has a working implementation multiple GT in the same quad? I'm trying to follow the following example found on the pg290-v-smpte-uhdsdi-rx-ss.pdf document.

Capture.JPG

Not all I/Os are connected in this capture so I'm not sure how to do it. Moreover, let say I need 4 GTs in the same quad. do you configure the slave GT with 3 links?

 

Many thanks.

 

Sébastien.

--Sebastien
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15 Replies
Moderator
Moderator
479 Views
Registered: ‎11-09-2015

Re: Implementation multiple GT in the same quad (SMPTE SDI)

Hi @sebo,

It depends on your requirements. If you need to have 4 separate lanes, then you need to have 1 master UHD_SDI GT and 3 slaves. All the slaves needs to be connected using the same way with the master (for qpll lock).

Let me know if you have any issues with this.

Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
Explorer
Explorer
474 Views
Registered: ‎03-17-2011

Re: Implementation multiple GT in the same quad (SMPTE SDI)

Hi @florentw

We are using the 4 lanes from a quad.

The entire cmp_gt_ctrl bus must not be connected from the master to the slaves?

Just the pll lock as mentioned in the figure?

Thanks.

 

S/

--Sebastien
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Moderator
Moderator
467 Views
Registered: ‎11-09-2015

Re: Implementation multiple GT in the same quad (SMPTE SDI)

Hi @sebo,

I believe the cmp_gt_ctrl bus should be connected to the same input as the master.

The bit 0 and 1 of cmp_gt_sts is giving you the QPLL lock status so this is what you need to connect to the slave.

The version 2018.3 of the PG290 is giving a better detail of each of the bit of both the control and status signal.

Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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Explorer
Explorer
460 Views
Registered: ‎03-17-2011

Re: Implementation multiple GT in the same quad (SMPTE SDI)

Do you have a working example?

For now we are using 2018.2. The GT master is one SDI link. The slave is configured is configured with 3 SDI links.

I don't find the document very clear.

--Sebastien
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Moderator
Moderator
455 Views
Registered: ‎11-09-2015

Re: Implementation multiple GT in the same quad (SMPTE SDI)

Hi @sebo,

I do not have a working example but I had customer successful so I know it can work.

Are you able to generate a bitsream or do you get any error in the earlier steps?

Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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Explorer
Explorer
452 Views
Registered: ‎03-17-2011

Re: Implementation multiple GT in the same quad (SMPTE SDI)

I was able to generate the bitfile. But it seems the rxoutclk/txoutclk for the slaves are not generated...

 

--Sebastien
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Moderator
Moderator
449 Views
Registered: ‎11-09-2015

Re: Implementation multiple GT in the same quad (SMPTE SDI)

Hi @sebo,

Could you try to add an ILA to the cmp_gt_sts of at least one slave? This should give information on whether the PLLs are locked.


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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Moderator
Moderator
371 Views
Registered: ‎11-09-2015

Re: Implementation multiple GT in the same quad (SMPTE SDI)

Hello @sebo,

Bonne Année 2019!

What is you current status on this? Did you make any progress?

Best Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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Explorer
Explorer
361 Views
Registered: ‎03-17-2011

Re: Implementation multiple GT in the same quad (SMPTE SDI)

Hi @florentw

Thanks for following this up. Bonne année 2019!

Yes we've made progress but we still have some tests to perform next week.

We were able to have a passthrough working on at least one GTH of the quad but not all of them.

I still need to investigate.

I'll keep you posted.

 

--Sebastien
Observer jribeiro_mog
Observer
314 Views
Registered: ‎11-19-2018

Re: Implementation multiple GT in the same quad (SMPTE SDI)

Hi @sebo,

 

I'm facing the same problem as you were previously, where rxoutclk and txoutclk don't seem to be generated properly, and since you seem to have figured it out, could you please share the solution as it might be the same issue in my design.

 

Thanks in advance,

José.

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Observer miguelcosta94
Observer
228 Views
Registered: ‎11-14-2018

Re: Implementation multiple GT in the same quad (SMPTE SDI)

Hi @sebo and @jribeiro_mog,

I'm experiencing exactly the same problem as you. @sebo could you please share the solution? I'm really struggling to solve the problem as the documentation is not very clear.

Best regards,

Miguel Costa

 

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Moderator
Moderator
224 Views
Registered: ‎11-09-2015

Re: Implementation multiple GT in the same quad (SMPTE SDI)

Hi @miguelcosta94 and @jribeiro_mog,

You should create a new topic for your issue. Not every design or issue will be the same.

Share screenshot of how you have done it.


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Explorer
Explorer
209 Views
Registered: ‎03-17-2011

Re: Implementation multiple GT in the same quad (SMPTE SDI)

Hi,

Will do but later as our debugging is not finished. We're migrating to 2018.3.

By the way, @florentw, in the IPI, can we use implement only one instance of the IP where we use 4 GTs?

For now, I do use 2 instances:

  • 1 instance as a master with PLLs included (include GT common in core) --> 1 GTHs
  • 1 instance as a slave with no PLLs included  --> 3 GTHs

Regards,

--Sebastien
Moderator
Moderator
199 Views
Registered: ‎11-09-2015

Re: Implementation multiple GT in the same quad (SMPTE SDI)

HI @sebo,

It depends on your system. If the 4 lanes are fully independent, I recommend to use 4 UHD SDI GT


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
Explorer
Explorer
187 Views
Registered: ‎03-17-2011

Re: Implementation multiple GT in the same quad (SMPTE SDI)

Well they're located in the same quad, each of them receiving independant SDI video and able to send SDI video in passthrough.

All four GTH, in the quad, share the same QPLL0 (Rx) and QPLL1 (Tx). We use an external PLL for jitter filtering.

 

--Sebastien
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