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Contributor
Contributor
772 Views
Registered: ‎08-29-2016

Incorrect Clock Speeds in MIPI Rx Simulation

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Hi,

I am using the MIPI CSI-Rx Subsystem IP in a design for the Virtex VCU118 Ultrascale+ Board.

So far I am just running behavioural simulations and post-synthesis functional simulations, using a System Verilog CSI-2 model to generate the incoming MIPI packets. the line rate (for the 4-lANE design) is set at 1188Mbps.

This should mean a mipi clock rate of : 594Mhz (period 1.683ns) and an rx_byte_clk_clk rate of 148.5Mhz (period 6.734ns ).

It seems that the clock constraints defined in the .xdc files under the MIPI IP wrapper are not correct - file 'bd_45e0_phy_0_ooc.xdc' shows the phy clock rate as 1.5 gbps (period of 0.667ns).

Is there a way to over-ride these preferences ? I can see in the behavioural and post-synthesis simulations that the output phy clock is not the set 1188 rate, but the incorrect faster rate.

The .xci file and the xdc files are attached.

IP Version: MIPI CSI-2 Rx Subsystem 2.2 (Rev. 1)

OS: Linux

Vivado Version: 2017.2

Board/Part: XCVU9P-FLGA2104-2L-E

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1 Solution

Accepted Solutions
Xilinx Employee
Xilinx Employee
710 Views
Registered: ‎03-30-2016

Re: Incorrect Clock Speeds in MIPI Rx Simulation

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Hello @gmoore

For your usecase (UltraScale+ device , RX only IP with continuous clock-mode)
I don't think we have any critical issue. ( A few customer are using 2016.4 IP with similar usecase in their product without any issue)

But please notice that MIPI CSI-2 RX Subsystem and MIPI D-PHY IP has many improvement since 2017.2 release. (You can check the IP change log in the Vivado).
Since you are doing a new design, I do suggest to use the latest MIPI IP.


Please check this Answer record. https://www.xilinx.com/support/answers/71582.html 
You will need to add  the following constraint if you are using MIPI IP from Vivado 2018.2 and previous version.

set_property DIFF_TERM_ADV TERM_100 [get_ports .... ]

 

Thanks & regards
Leo

6 Replies
Xilinx Employee
Xilinx Employee
727 Views
Registered: ‎03-30-2016

Re: Incorrect Clock Speeds in MIPI Rx Simulation

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Hello @gmoore

1500Mbps clock constraint is expected.

Note :
If you are using MIPI IP for UltraScale+ device, please use 2018.1 or newer IP version.
( IP from Vivado 2018.3 is recommended )
There is a critical issue in the older MIPI IP that your system may not work correctly with non-continous clock mode.


Thanks & regards
Leo

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Contributor
Contributor
721 Views
Registered: ‎08-29-2016

Re: Incorrect Clock Speeds in MIPI Rx Simulation

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Hi Karnanl,

Thank you for the response. For compatibility reasons I would like to stay with my current version of the IP - in my case, I am using continuous clock mode - are there any known issues with using continuous clock mode in my current version of the IP ? 

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Xilinx Employee
Xilinx Employee
711 Views
Registered: ‎03-30-2016

Re: Incorrect Clock Speeds in MIPI Rx Simulation

Jump to solution

Hello @gmoore

For your usecase (UltraScale+ device , RX only IP with continuous clock-mode)
I don't think we have any critical issue. ( A few customer are using 2016.4 IP with similar usecase in their product without any issue)

But please notice that MIPI CSI-2 RX Subsystem and MIPI D-PHY IP has many improvement since 2017.2 release. (You can check the IP change log in the Vivado).
Since you are doing a new design, I do suggest to use the latest MIPI IP.


Please check this Answer record. https://www.xilinx.com/support/answers/71582.html 
You will need to add  the following constraint if you are using MIPI IP from Vivado 2018.2 and previous version.

set_property DIFF_TERM_ADV TERM_100 [get_ports .... ]

 

Thanks & regards
Leo

Moderator
Moderator
628 Views
Registered: ‎11-09-2015

Re: Incorrect Clock Speeds in MIPI Rx Simulation

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Hi @gmoore,

Is everything clear for you? Was @karnanl's reply enough for you?

If your question is answered or your issue is solved, please kindly mark the response which helped as solution (click on "Accept as solution" button below the reply)

If this is not solved/answered, please reply in the topic giving more information on your current status.

Thanks and Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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Contributor
Contributor
567 Views
Registered: ‎08-29-2016

Re: Incorrect Clock Speeds in MIPI Rx Simulation

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Apologies for the delayed response. 

In my case, defining the actual constraints in the top-level constraints file over-rode the constraints which had been generated in the IP constraints file, and gave me the correct clock speeds. 

 

You may close this ticket. 

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Moderator
Moderator
565 Views
Registered: ‎11-09-2015

Re: Incorrect Clock Speeds in MIPI Rx Simulation

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Hi @gmoore,

Could you kindly mark @karnanl's reply as accepted solution (click on accept as solution below the reply). We want to avoid Xilinx action on this and prefer when the user marks as solution ;)


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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