UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Highlighted
Contributor
Contributor
338 Views
Registered: ‎11-27-2018

Inferred Bitslice Ports in MIPI RX core

Hi,

     It is mentioned in MIPI RX subsystem product guide that "bg<x>_pin<y>_nc The core infers bitslice0 of a nibble for strobe propagation within the byte group; <x> indicates byte group (0,1,2,3); <y> indicates bitslice0 position (0 for the lower nibble, 6 for the upper nibble)"

In my design the input ports that I see are bg1_pin0_nc and bg3_pin0_nc for a given set of IO assignments.

Does it mean that these particular inferred pins cant be used elsewhere in the design?

Tags (1)
0 Kudos
2 Replies
Xilinx Employee
Xilinx Employee
300 Views
Registered: ‎03-30-2016

Re: Inferred Bitslice Ports in MIPI RX core

Hello Mohan @msattine 

Yes, your understanding is correct.

Thanks & regards
Leo

0 Kudos
Moderator
Moderator
273 Views
Registered: ‎11-09-2015

Re: Inferred Bitslice Ports in MIPI RX core

Hi @msattine 

Is everything clear for you on this topic?

If your question is answered or your issue is solved, please kindly mark the response which helped as solution (click on "Accept as solution" button below the reply)

If this is not solved/answered, please reply in the topic giving more information on your current status.

Thanks and Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
0 Kudos