UPGRADE YOUR BROWSER
We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!
03-01-2013 01:31 PM
Hi,
Currently I'm trying to implement this core with the VmodCam and Atlys Board, I think that firstly I generate a RGBtoYCrCb core, to work with the Edge filter, but nothing happens with the output signals, so I generate a YCrCbtoRGB, but when the Edge core is connect it doesn't work. Is there a problem with the clock? or what is the correct configuration, I'm using this core as a "constant". I've been working just with the RGBtoYCrCb and viceverse and it works.
Do I have to use a DCM(Clocking Wizzard Core) to control the clocks? or what could be the problem. I hope you can guide me with this topic.
thanks.
03-06-2013 02:12 PM
Hi,
Could it be the problem , that I'm using the version 2.0 of Edge?..or Have I to use Axi4 interface?...
I hope anybody can help me with this topic, is for my thesis.
thanks.
03-29-2013 11:39 AM
04-01-2013 04:59 PM
Hi,
Could you send me the bit file to try it....about the clock, which one would be correct value, I've been trying to configure a DCM, and which the values of the hsync and vsync signals?..
Thanks.