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Visitor hisharry
Visitor
7,952 Views
Registered: ‎03-04-2008

Is it possible to include the DDR controller as a block in System Generator?

Hi all,
 
My program need a large memory. I find the example "ml402_mpeg4_dec" uses extenal DDR as a pcore.
Can we just include those VHDL codes(or from other source?) as a Blackbox and then use in hardware co-simulation?
 
If so, we can debug and test very easy.
Thanks for suggestions.
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4 Replies
Xilinx Employee
Xilinx Employee
7,938 Views
Registered: ‎08-02-2007

Re: Is it possible to include the DDR controller as a block in System Generator?

This may be possible, but more work than exporting the System Generator design.  There would be several hurdles in trying to run hardware co-sim with a DDR controller (assuming you are using MIG):

1. There are particular constraints that you will need for the PHY interface (such as timing, IOStandard, etc).
2. There are particular synthesis / implementation options you should be using for the controller.
3. The timing parameters of the controller / memory part would need to be maintained.

The first two issues could have potential solutions with varying degrees of effort, but there is no direct flow for accomplishing this.  The third issue would pose the biggest problem.  Because of the timing parameters associated with the controller/memory part, single-stepped hardware co-sim would not work.  You would need to use a free-running clock, but this has additional problems associated with it.

A simplier approach would be to write a synthesizable testbench that you could use to test the System Generator and DDR controller design.
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Visitor hisharry
Visitor
7,927 Views
Registered: ‎03-04-2008

Re: Is it possible to include the DDR controller as a block in System Generator?

Thanks for your useful reply.
However, ISE EDK MIG... is not easy as System Generator for software/DSP engineer.
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Visitor hisharry
Visitor
7,910 Views
Registered: ‎03-04-2008

Re: Is it possible to include the DDR controller as a block in System Generator?

In P24 of ug217,
"The controller contains a simulation model and can be run in HDL co-simulation mode, or compiled to run in real time and as part of hardware co-simulation block"
I am wondering how to "compiled to run in real time and as part of hardware co-simulation block".
Can anyone give me further information?
Thanks.
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Xilinx Employee
Xilinx Employee
7,858 Views
Registered: ‎08-07-2007

Re: Is it possible to include the DDR controller as a block in System Generator?

One difficulty you'll likely encounter is that most memory controllers use bi-directional IO as well as multiple clocks on occasion.  The SysGen HDL black box interface does not currently support bi-directional signals for top level ports and all clocks are driven by a single system clock.

As was pointed out, this type of complex HDL design is better suited for integration in ISE after you've generated the DSP portion of your design. 
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