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Adventurer
Adventurer
3,084 Views
Registered: ‎02-14-2009

Is timing detection in VTC core broken?

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Hi!

 

Here is simplified project with VTC and VGA timing generator only.
All 5 (hs,vs,vb,hb,active_video) signals are connected to VTC.
External reset realised via testbench (low during 5 clock cycles).
VGA timing is classic 640x480 (full frame 800x525, HS position - 16-96-48, VS position - 10-2-33).
All video signals are active-high.
Clock signal set to 10ns, so all intervals can be easily measured.

Vivado 2017.3, VTC core version Version 6.1 (Rev. 11) .

 

Result : VTC is unable to lock based on input stream.

 

Could you please help me with this issue?

BD exported in TCL. All screens are attached. VGA timing generator source file is attached.

 

Thanks!

 

Topic with similar VTC behaviour:
https://forums.xilinx.com/t5/General-Technical-Discussion/VTC-generation-based-on-detection-isnt-working/td-p/641739

 

block_design.PNG
vtc settings.PNG
vga_frame_timing.PNG
results.PNG
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1 Solution

Accepted Solutions
Adventurer
Adventurer
4,473 Views
Registered: ‎02-14-2009

Re: Is timing detection in VTC core broken?

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Also here is my summary about usage of VTC core:

 

1. incoming hblank should be deassert (previous post) during incoming vblank otherwise VTC detector can not achive lock state.

 

2. incoming hblank should toggle during incoming vblank otherwise VTC generator unable to work even if detector side can achive lock state.

 

3. VTC detector is able to lock with only 3 incoming signals (av/hb/vb or av/hs/vs). ("The detection typically requires three to five input video frames to detect and lock." - it is expected behaviuor described in VTC product guide)

 

4. VTC generator is unable to reproduce 5 (av/hb/vb/hs/vs) signals from 3 (av/hb/vb) - generated hs and vs in this case will have 1 clock long and 1 line long respectively. Generation of 5 signals is available only from av/hs/vs combination. AR# 39413 :

 

"It can regenerate Vertical Blank, Horizontal Blank and Active Video, if you provide the following inputs:
•Vertical Blank and Horizontal Blank
•Vertical Blank, Horizontal Blank, and Active Video

It can generate Vertical Blank, Horizontal Blank, Vertical Sync, Horizontal Sync, and Active Video, if you have the following input combinations:
•Vertical Sync, Horizontal Sync, and Active Video
•Vertical Blank, Horizontal Blank, Vertical Sync, Horizontal Sync, and Active Video"

 

5. It is impossible to have hblank at the end of line when you are using VTC as detector and generator. In this case vblank signal goes to active state but later will never be de-asserted. This behaviour was observed in this thread too https://forums.xilinx.com/t5/General-Technical-Discussion/VTC-generation-based-on-detection-isnt-working/td-p/641739 (link from 1 post), but I was able to reproduce it in simulation. AR# 69227 :

 

"Setting VBLANK to de-assert at the same time as HBLANK on the last line of the frame is not supported."

 


Link to 4 and 5 should be definitely exist in product guide of VTC core!

vblank_error.PNG
10 Replies
Moderator
Moderator
2,998 Views
Registered: ‎11-09-2015

Re: Is timing detection in VTC core broken?

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Hi @toshas,

 

Could you zoom a bit on you waveform? I want to see only one frame?

 

What timing did you use? How long is you hblank, vblank? How many time do you wait between vblank strat and vsync start? And for hblank and vsync?


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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Adventurer
Adventurer
2,994 Views
Registered: ‎02-14-2009

Re: Is timing detection in VTC core broken?

Jump to solution

Hi ,

 

Sure! Here it is:

full frame size 525lines.PNG
full line size 800pix.PNG
hblank size 160pix.PNG
hsync size 16-96-48pix.PNG
vblank size 45lines.PNG
vsync size 10-2-33lines.PNG
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Adventurer
Adventurer
2,993 Views
Registered: ‎02-14-2009

Re: Is timing detection in VTC core broken?

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zipped files

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Moderator
Moderator
2,975 Views
Registered: ‎11-09-2015

Re: Is timing detection in VTC core broken?

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Hi @toshas,

 

I think I have found what is wrong. As per this website, for 640 x 480 you are supposed to use negative pulse for hsync and vsync while you are using positive pulses.

 

Could you try to invert them?

 

Hope that helps,

 

Regards,

 

Florent


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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Adventurer
Adventurer
2,971 Views
Registered: ‎02-14-2009

Re: Is timing detection in VTC core broken?

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Hi ,

 

Thanks for the reply! 

 

Done! Result is the same.

 

By the way in PG016 stated that VTC core supports "Automatic detection of input video control signal polarities".

So it seems like polarity isn't very important, I'm right ?

inv_hs_vs.PNG
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Moderator
Moderator
2,963 Views
Registered: ‎11-09-2015

Re: Is timing detection in VTC core broken?

Jump to solution

Hi @toshas,

 

By the way in PG016 stated that VTC core supports "Automatic detection of input video control signal polarities".

So it seems like polarity isn't very important, I'm right ?

Not really. This means that you do not have to tell the polarity to the VTC however you have to follow the spec for the polarity.

 

Could you try to also invert Vblank and hbank to nagative pulse (you will need to change your logic for video active)?

 

If this is still not working, could you try to add a VTC as generator for 640x480 and see if the VTC as detector can detect the format? It could help seeing what is wrong (I am not saying that this is not an issue with the VTC).

 

Regards,

 

Florent


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
Adventurer
Adventurer
2,949 Views
Registered: ‎02-14-2009

Re: Is timing detection in VTC core broken?

Jump to solution

"Not really. This means that you do not have to tell the polarity to the VTC however you have to follow the spec for the polarity."

 

Now it's clear. Thanks!

 

"Could you try to also invert Vblank and hbank to nagative pulse (you will need to change your logic for video active)?"

 

Waveform slightly changed but there is no luck with lock.

 

"If this is still not working, could you try to add a VTC as generator for 640x480 and see if the VTC as detector can detect the format? It could help seeing what is wrong (I am not saying that this is not an issue with the VTC)."

 

I will try this too. Thanks!

inv_hb_vb.PNG
av_change.PNG
new_bd.PNG
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Adventurer
Adventurer
2,907 Views
Registered: ‎02-14-2009

Re: Is timing detection in VTC core broken?

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Hi ,

 

Success! Excellent idea to add VTC as generator!


In my VGA generator hblank was set during vblank, it is wrong behaviour.
Now it is fixed and I am able to get lock with 5 active signals.

hb_wrong.PNG
hb_right.PNG
0 Kudos
Adventurer
Adventurer
4,474 Views
Registered: ‎02-14-2009

Re: Is timing detection in VTC core broken?

Jump to solution

Also here is my summary about usage of VTC core:

 

1. incoming hblank should be deassert (previous post) during incoming vblank otherwise VTC detector can not achive lock state.

 

2. incoming hblank should toggle during incoming vblank otherwise VTC generator unable to work even if detector side can achive lock state.

 

3. VTC detector is able to lock with only 3 incoming signals (av/hb/vb or av/hs/vs). ("The detection typically requires three to five input video frames to detect and lock." - it is expected behaviuor described in VTC product guide)

 

4. VTC generator is unable to reproduce 5 (av/hb/vb/hs/vs) signals from 3 (av/hb/vb) - generated hs and vs in this case will have 1 clock long and 1 line long respectively. Generation of 5 signals is available only from av/hs/vs combination. AR# 39413 :

 

"It can regenerate Vertical Blank, Horizontal Blank and Active Video, if you provide the following inputs:
•Vertical Blank and Horizontal Blank
•Vertical Blank, Horizontal Blank, and Active Video

It can generate Vertical Blank, Horizontal Blank, Vertical Sync, Horizontal Sync, and Active Video, if you have the following input combinations:
•Vertical Sync, Horizontal Sync, and Active Video
•Vertical Blank, Horizontal Blank, Vertical Sync, Horizontal Sync, and Active Video"

 

5. It is impossible to have hblank at the end of line when you are using VTC as detector and generator. In this case vblank signal goes to active state but later will never be de-asserted. This behaviour was observed in this thread too https://forums.xilinx.com/t5/General-Technical-Discussion/VTC-generation-based-on-detection-isnt-working/td-p/641739 (link from 1 post), but I was able to reproduce it in simulation. AR# 69227 :

 

"Setting VBLANK to de-assert at the same time as HBLANK on the last line of the frame is not supported."

 


Link to 4 and 5 should be definitely exist in product guide of VTC core!

vblank_error.PNG
Moderator
Moderator
972 Views
Registered: ‎11-09-2015

Re: Is timing detection in VTC core broken?

Jump to solution

Hi @toshas,

 

Happy to know that it is working now for you. And thank you for sharing your results (plus the AR numbers) to the community. Your post is a great value (so it deserve kudos).

 

Could you just mark it as a solution to close the thread? It could help users to find the same responses.

 

I have asked a change in the documentation. However, I am not sure when the modification will be.

 

Best Regards,

 

Florent


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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