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Observer r1200gsa
Observer
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Registered: ‎03-15-2018

Issue with DP 1.2 TX subsystem SST

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Hello, We are trying to use the DisplayPort TX subsystem IP (according to PG199).The hardware is based on ZCU102 + Inrevium TB3 FMC mezzanine. In the first phase we started from the reference design, which works fine. We get some issue with the second phase. In this phase, we don't use the Video Pattern Generator anymore , but a VDMA which transfers two  memory contains (MM2S). The format used is RGB 24 bit color pixel. The main lanes training seems to work. 4 Lanes used work at 2.7 Gbps (limited by the screen) , the DP core is programmed to 8 bpc, 4 pixels per clock cycle. The axi stream clock runs at 150Mhz. The VDMA is programmed to transfer them to DP TX subsystem. We tried to keep the BSP software to initialize the TX subsystem. We have instrumented DP axis stream input  with ILA and  we can see pixel transfers as expected.  We can read the EDID information from the sink device (the  screen).  We see pixels entering in a regular manner in the DP core drived by VDMA. We have compared the values in registers between the reference design and our application and didn't find difference until now. All seems to work fine but unfortunately, the screen wakes up  when our program starts but go back to the standby mode after initialization and no image is displayed. In the ila waveform (150Mhz) , we can see a very short time (76 clock cycles) between the last EOL and the start of frame (this time seems to be due only to DMA). Do we have to synchronize the DP IP core with the VMDA using mm2s_fsync but in this case which device drives this signal ? Could you help us to understand what's happening or to verify some points we have forget ? Thanks, Philippe
vdma_dptxss.jpg
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Observer r1200gsa
Observer
343 Views
Registered: ‎03-15-2018

Re: Issue with DP 1.2 TX subsystem SST

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Hi Florent,

It was the good way.

However, we have spent a lot of time understanding the problem.

The XILINX TX reference design adjust the value of the AXIS clock (stream between the VPG and DP core). This value is calculated and programmed into the clock_wizard IP by a function ComputeMandD() and this function is embedded in the video pattern generator software.

When we did switched to a VDMA design , we did removed the TPG and the associated software. We didn't anymore call the function and it was the problem. Then we have extracted the function from the video pattern generator software and used it alone in our initialization and now it works fine.

... and the FIFO overflow status bit is now always at 0.

We can now continue our adventure and try to acquire a DP stream.

Thanks for your help

Philippe

18 Replies
Moderator
Moderator
591 Views
Registered: ‎11-09-2015

Re: Issue with DP 1.2 TX subsystem SST

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Hi @r1200gsa ,

First thing I need to mention is that if you are using 2018.3, you might want to make sure that you are aware of the issue mentioned in https://www.xilinx.com/support/answers/72322.html

I do not think this is the issue you are getting but I prefer to warn you about this.

Then about your issue. You need to be aware that you do not distribute the data the same way depending on the how maly lanes are used (and the USER_PIXEL_WIDTH value (reg 0x1B8)). Refer to the table 2-1. If you do not have any logic in your design to accomodate this, this will certainly be an issue for you.

If you check the path-through example design for the KC705 or KCU105 (using the VDMA), you will see that the video stream coming from RX is going through the Video Pattern Generator which is taking care of the remaping.

For the ZCU102 example design, a remapper IP is used for this purpose.

If you assume you are always trained at 4 lanes (and USER_PIXEL_WIDTH=4) you will probably face issues because you will not have enough data at the input.

Back to the example design for the KC705, you can clearly see that you do not need a fsync signal. The read the data as soon as it is ready.


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Observer r1200gsa
Observer
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Registered: ‎03-15-2018

Re: Issue with DP 1.2 TX subsystem SST

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Hi Florent,

Thanks for your answer.

Concerning your first advice, we have the correct frequency value (269,98 Mhz) for TXOUTCLK  in the clock networks report.

However I don't understand very well when you say "you do not distribute the data the same way depending on the how many lanes are used". Are you talking about pixel organisation in DDR4 RAM ?  for instance : RGB vs RBG ?

Do you think this kind of error can put the monitor in idle mode ? (which currently is our issue)

To verify the VDMA task,  (without worrying the drawing we get) we have encoded Row&Column number on each 24 bits pixel (MSB 12 bits for Row and LSB 12 bits for column), with ILA we can see each  96 bits value ( 0x3,0x2,0x1,0x0 for the first value at SOF)  and (0x43777f,0x43777e,0x43777d, 0x43777c) [which is corresponding to the programmed resolution 1080x1920] for the last value with LAST axi signal at the end of frame.Currently the VDMA is programmed in parked mode with only one memory page.

When you wrote "The read the data as soon as it is ready." I have to understand : " The DP TX subsystem reads the data as soon as it is ready " ?

Regards.

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Moderator
Moderator
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Registered: ‎11-09-2015

Re: Issue with DP 1.2 TX subsystem SST

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Hi @r1200gsa 


@r1200gsa wrote:

Hi Florent,

Thanks for your answer.

Concerning your first advice, we have the correct frequency value (269,98 Mhz) for TXOUTCLK  in the clock networks report.

However I don't understand very well when you say "you do not distribute the data the same way depending on the how many lanes are used". Are you talking about pixel organisation in DDR4 RAM ?  for instance : RGB vs RBG ?

[Florent] - No I am talking on the AXI4-Stream going through the DP TX core. You need to map the data depending on how many lanes are trained. The VDMA will not work directly. If you have 4 lanes trained, you can send 4 pixels at the time. But if you have lonly one lane trained, you can only send one pixel per clock. Refer to table 2-1 of PG199

Do you think this kind of error can put the monitor in idle mode ? (which currently is our issue)

[Florent] - The displayport might not send the data if it is incorrect which might stop the training and put tyhe monitor in sleep mode

To verify the VDMA task,  (without worrying the drawing we get) we have encoded Row&Column number on each 24 bits pixel (MSB 12 bits for Row and LSB 12 bits for column), with ILA we can see each  96 bits value ( 0x3,0x2,0x1,0x0 for the first value at SOF)  and (0x43777f,0x43777e,0x43777d, 0x43777c) [which is corresponding to the programmed resolution 1080x1920] for the last value with LAST axi signal at the end of frame.Currently the VDMA is programmed in parked mode with only one memory page.

When you wrote "The read the data as soon as it is ready." I have to understand : " The DP TX subsystem reads the data as soon as it is ready " ?

[Florent] - Yes

Regards.





Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Observer r1200gsa
Observer
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Registered: ‎03-15-2018

Re: Issue with DP 1.2 TX subsystem SST

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We have 4 lanes trained but,  as you can see in our design attached to my previous post, we have a 96 bits datapath  (4 pixels / clock cycle) from the VDMA (AXIS - MM2S port) to the DP subsystem. Do we have to make another configuration or operation ?

 

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Moderator
Moderator
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Registered: ‎11-09-2015

Re: Issue with DP 1.2 TX subsystem SST

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Hi @r1200gsa ,

Are you sure you have 4 lanes trained? Also even if you have 4 lane trained, you still depend on USER_PIXEL_WIDTH. What is the value of USER_PIXEL_WIDTH?


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Observer r1200gsa
Observer
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Registered: ‎03-15-2018

Re: Issue with DP 1.2 TX subsystem SST

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The PLL LOck Status register (0ffset 0x18)  = 0x20 (QPLL1LOCK it seems correct because we are on Ultrascale+ device)

The PHY register TX_INITIALIZATION (offset 0x1C) = 0x08080808 (TxReady for each channel)

The PHY register TX_INITIALIZATION_STATUS (0x20) = 0x07070707 (TxResetDone, TXPMAResetDone, GTpowerGood)

 

Regarding USER_PIXEL_WITDH (offset 0x1B8 of DP Core ) the value is 4.

To set this value , we have programmed the XDp_TxMainStreamAttributes structure with UserPixelWidth member and OverrideUserPixelWidth member.

 

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Moderator
Moderator
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Registered: ‎11-09-2015

Re: Issue with DP 1.2 TX subsystem SST

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Hi @r1200gsa ,

Can you share the ILA data when there is no more data going from the VDMA to DP core. Just to check if my guess (that this is pending on DP core, i.e. TREADY is low) is correct?

Also could you share both the register dumps of DP and VPHY IPs?


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Observer r1200gsa
Observer
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Registered: ‎03-15-2018

Re: Issue with DP 1.2 TX subsystem SST

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Florent,

I have attached a waveform from ILA. I have triggered on start of frame in middle position of window. You can see TREADY go low after 4 lines (4 TLAST) for a long time.

I 'm still working to dump the DP and PHY registers.

Philippe.

 

zcu102-vdma-dp.jpg
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Moderator
Moderator
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Registered: ‎11-09-2015

Re: Issue with DP 1.2 TX subsystem SST

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Hi @r1200gsa ,

As TREADY is going low, you know that you need to investigate on the DP side and not on the VDMA.

Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Observer r1200gsa
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Registered: ‎03-15-2018

Re: Issue with DP 1.2 TX subsystem SST

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florent,

please find attached the DP core and Vphy registers.

 

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Moderator
Moderator
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Registered: ‎11-09-2015

Re: Issue with DP 1.2 TX subsystem SST

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Hi @r1200gsa ,

Looking at your register dumps this is what I only note:

reg 0x110 = 1 -> this means that there is a FIFO overflow. You might want to read it again multiple to see if the bit is cleared or if the error is consistent

I would also look at the VDMA, make sure it is proprly configured for 1920x1080


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Observer r1200gsa
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Registered: ‎03-15-2018

Re: Issue with DP 1.2 TX subsystem SST

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Following is the programming of VDMA registers (only read channel used currently)

VDMA - CR = 0x00010001
VDMA - SR = 0x00010000
VDMA - MM2S_START_ADDRESS = 0x01386000
VDMA - MM2S_START_ADDRESS = 0x01975000 (not used currently)
VDMA - MM2S_HSIZE = 5760
VDMA - MM2S_VSIZE = 1080
VDMA - STRIDE = 5760

 

 

The Vertical size

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Observer r1200gsa
Observer
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Registered: ‎03-15-2018

Re: Issue with DP 1.2 TX subsystem SST

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However , when I read periodically the register TX_USER_FIFO_OVERFLOW (offset 0x110) is always at 1...

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Moderator
Moderator
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Registered: ‎11-09-2015

Re: Issue with DP 1.2 TX subsystem SST

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Hi @r1200gsa ,

You might want to compare the register dumps with the one from the example design to find out the differences.

Regards


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Moderator
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Registered: ‎11-09-2015

Re: Issue with DP 1.2 TX subsystem SST

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Hi @r1200gsa ,

Do you have any updae on this? Were you able to make any progress?


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Observer r1200gsa
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Registered: ‎03-15-2018

Re: Issue with DP 1.2 TX subsystem SST

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Hi Florent,

 

I'll continue testing next Monday

I'll try to reduce the frequency of the video stream from VDMA to DP (from 150 Mhz to 75Mhz) or to divide the number of pixels per clock cycle (from 4 to 2) 

and see if the overflow fifo signal is still present.

 I will post the result at this time

Philippe

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Observer r1200gsa
Observer
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Registered: ‎03-15-2018

Re: Issue with DP 1.2 TX subsystem SST

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Hi Florent,

It was the good way.

However, we have spent a lot of time understanding the problem.

The XILINX TX reference design adjust the value of the AXIS clock (stream between the VPG and DP core). This value is calculated and programmed into the clock_wizard IP by a function ComputeMandD() and this function is embedded in the video pattern generator software.

When we did switched to a VDMA design , we did removed the TPG and the associated software. We didn't anymore call the function and it was the problem. Then we have extracted the function from the video pattern generator software and used it alone in our initialization and now it works fine.

... and the FIFO overflow status bit is now always at 0.

We can now continue our adventure and try to acquire a DP stream.

Thanks for your help

Philippe

Moderator
Moderator
330 Views
Registered: ‎11-09-2015

Re: Issue with DP 1.2 TX subsystem SST

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HI @r1200gsa ,

Good to know that you were able to solve your issue.

I agree with you the example design is not the easiest to understand. I have already requested more details in the doc. Hopefully it will come soon.

Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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