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Observer baring42read
Observer
409 Views
Registered: ‎08-28-2019

Issues concerning mm2s_Tready(VDMA IP)

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I have being trying to understand the functioniin of VDMA IP. So, connected the VDMA IP to a TPG and and the AXI to Video out IP. Everything is working as expected and frames are being displayed. But, the mm2s_Tready is not constantly asserted after TValid is asserted  asn explained in the VDMA IP documenation as shown below.

Capture1.PNG

I read from the forum that, the slave is not ready to accept the data and that's the reason the Tready  is not constant High. My question is, what can cause the IP (AXI to Video out) which generates trhe mm2s_tready signal to not be ready to accept the signal?. The waveform form my designa dn the block design are shown below.

The stream frequency is 100Mhz and the pixel clock frequency is 40Mhz(for 800x600 frame resolution).

Capture.PNGCapture2.PNG

 

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Contributor
Contributor
358 Views
Registered: ‎11-18-2012

Re: Issues concerning mm2s_Tready(VDMA IP)

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The reason is frequency. Pixel Clock is 40MHz, Stream is 100MHz.
In other words, ready goes low once in 2.5 Cycle @ 100 MHz.
Since the Video side also has Blanking, the ready should be low more often.

If the frequency of Stream is lowered, I think whether the frequency that ready becomes Low will decrease.

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Contributor
Contributor
359 Views
Registered: ‎11-18-2012

Re: Issues concerning mm2s_Tready(VDMA IP)

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The reason is frequency. Pixel Clock is 40MHz, Stream is 100MHz.
In other words, ready goes low once in 2.5 Cycle @ 100 MHz.
Since the Video side also has Blanking, the ready should be low more often.

If the frequency of Stream is lowered, I think whether the frequency that ready becomes Low will decrease.

Observer baring42read
Observer
282 Views
Registered: ‎08-28-2019

Re: Issues concerning mm2s_Tready(VDMA IP)

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Thank you for this insightful  answer. It makes everything very clear now. If you have many IPs in the pipeline, this can affect the last few IPs right(for example, last two IPs) right? I had a block design, trying to to check the throughput of the HP port . So, I connected two three VDMAS(in Cascade) with other series of IPs. The last IP of the pipeline before the axi to video out IP was the rgb2ycbcr. Its Tready was not constanly High reason being that the pixel clk frequency was 40Mhz. But the IP just before it was a VDMA and it's Tready was not constantly High too but it remains High longer than that of rgb2ycbcr as shown below. 

Capture3.PNG

Contributor
Contributor
239 Views
Registered: ‎11-18-2012

Re: Issues concerning mm2s_Tready(VDMA IP)

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Your understanding is almost right.
The correct understanding is that the ready input to the master is affected not only by the last few IPs, but also by the readiness of all subsequent IPs in the pipeline.

 

I saw the waveform. Although the IP output by axi to video out IP and the tready High period output by rgb2ycbcr IP seem to be different,
they are actually the same. Since 5Cycle is High for 2Cycle, I think that the average value is the same.

Depending on the type of IP, even if tready entered from the subsequent stage is fixed to High, the tready output by that IP is not necessarily fixed to High.
It depends on the logic and control method of IP.

Please ask if you have any other questions.