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Explorer
Explorer
1,293 Views
Registered: ‎10-18-2017

Linux Video PHY Driver Fail to Parse Device Tree

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Hello, I am trying to create a design to push image data to HDMI output on ZCU104. Currently, I am trying to ensure that the DRM KMS stack is probing properly at boot time. At boot time I have an HDMI output connected to the ZCU104. My best efforts at configuring the DRM KMS Stack in the kernel have led to this.

[    4.973976] xilinx_vphy: loading out-of-tree module taints kernel.
[    4.974638] xilinx_vphy: loading out-of-tree module taints kernel.
[    4.976429] xilinx-vphy a0010000.vid_phy_controller: probed
[    4.976438] xilinx-vphy a0010000.vid_phy_controller: Error parsing device tree
[    4.976450] xilinx-vphy: probe of a0010000.vid_phy_controller failed with error -22
[    5.036786] xlnx-drm-hdmi a0020000.v_hdmi_tx_ss: probed
[    5.042015] xlnx-drm-hdmi a0020000.v_hdmi_tx_ss: failed to get phy lane hdmi-phy0 index 0, error -19
[    5.051107] xlnx-drm-hdmi a0020000.v_hdmi_tx_ss: probe failed:: error_phy:

Here are the device tree properties PetaLinux tools generated for my Linux distro for both HDMI and Video PHY cores.

v_hdmi_tx_ss_0: v_hdmi_tx_ss@a0020000 {
			compatible = "xlnx,v-hdmi-tx-ss-3.1";
			reg = <0x0 0xa0020000 0x0 0x20000>;
			xlnx,add-mark-dbg = "false";
			xlnx,addr-width = <0xa>;
			xlnx,exdes-axilite-freq = <0x64>;
			xlnx,exdes-nidru = "true";
			xlnx,exdes-rx-pll-selection = <0x0>;
			xlnx,exdes-topology = <0x0>;
			xlnx,exdes-tx-pll-selection = <0x6>;
			xlnx,hdmi-fast-switch = "false";
			xlnx,hdmi-version = <0x3>;
			xlnx,hpd-invert = "false";
			xlnx,hysteresis-level = <0xc>;
			xlnx,include-hdcp-1-4 = "false";
			xlnx,include-hdcp-2-2 = "false";
			xlnx,include-low-reso-vid = "false";
			xlnx,include-yuv420-sup = "false";
			xlnx,input-pixels-per-clock = <0x2>;
			xlnx,max-bits-per-component = <0x8>;
			xlnx,validation-enable = "false";
			xlnx,vid-interface = <0x0>;
			xlnx,video-mask-enable = <0x1>;
		};
		vid_phy_controller_0: vid_phy_controller@a0010000 {
			compatible = "xlnx,vid-phy-controller-2.2";
			reg = <0x0 0xa0010000 0x0 0x10000>;
			xlnx,axi4lite-enable = "true";
			xlnx,component-name = "design_1_vid_phy_controller_0_0";
			xlnx,device = "xczu7ev";
			xlnx,dru-gain-g1 = <0x9>;
			xlnx,dru-gain-g1-p = <0x10>;
			xlnx,dru-gain-g2 = <0x4>;
			xlnx,dru-refclk-fabric-buffer = "none";
			xlnx,err-irq-en = <0x0>;
			xlnx,for-upgrade-architecture = "zynquplus";
			xlnx,for-upgrade-device = "xczu7ev";
			xlnx,for-upgrade-maxoptvol = "0.876";
			xlnx,for-upgrade-package = "ffvc1156";
			xlnx,for-upgrade-part = "xczu7ev-ffvc1156-2-e";
			xlnx,for-upgrade-refvol = "0.850";
			xlnx,for-upgrade-speedgrade = "-2";
			xlnx,hdmi-fast-switch = <0x1>;
			xlnx,input-pixels-per-clock = <0x2>;
			xlnx,int-hdmi-ver-cmptble = <0x3>;
			xlnx,nidru = <0x0>;
			xlnx,nidru-refclk-sel = <0x0>;
			xlnx,rx-gt-debug-ports = "false";
			xlnx,rx-no-of-channels = <0x3>;
			xlnx,rx-outclk-buffer = "none";
			xlnx,rx-pll-selection = <0x0>;
			xlnx,rx-protocol = <0x3>;
			xlnx,rx-refclk-sel = <0x0>;
			xlnx,rx-sb-ports = "true";
			xlnx,rx-tmds-clk-buffer = "bufg";
			xlnx,rx-video-clk-buffer = "bufg";
			xlnx,silicon-revision = <0x0>;
			xlnx,speedgrade = "-2";
			xlnx,supportlevel = <0x1>;
			xlnx,transceivercontrol = "false";
			xlnx,tx-gt-debug-ports = "false";
			xlnx,tx-no-of-channels = <0x3>;
			xlnx,tx-outclk-buffer = "none";
			xlnx,tx-pll-selection = <0x6>;
			xlnx,tx-protocol = <0x1>;
			xlnx,tx-refclk-fabric-buffer = "none";
			xlnx,tx-refclk-sel = <0x1>;
			xlnx,tx-sb-ports = "true";
			xlnx,tx-tmds-clk-buffer = "bufg";
			xlnx,tx-video-clk-buffer = "bufg";
			xlnx,txpi-port-en = "false";
			xlnx,txrefclk-rdy-invert = <0x0>;
			xlnx,use-gt-ch4-hdmi = <0x0>;
			xlnx,use-oddr-for-tmds-clkout = "true";
			xlnx,vid-phy-axi4lite-addr-width = <0xa>;
			xlnx,vid-phy-axi4lite-data-width = <0x20>;
			xlnx,vid-phy-control-sb-rx-tdata-width = <0x1>;
			xlnx,vid-phy-control-sb-tx-tdata-width = <0x1>;
			xlnx,vid-phy-rx-axi4s-ch-int-tdata-width = <0x14>;
			xlnx,vid-phy-rx-axi4s-ch-tdata-width = <0x14>;
			xlnx,vid-phy-rx-axi4s-ch-tuser-width = <0x1>;
			xlnx,vid-phy-status-sb-rx-tdata-width = <0x1>;
			xlnx,vid-phy-status-sb-tx-tdata-width = <0x2>;
			xlnx,vid-phy-tx-axi4s-ch-int-tdata-width = <0x14>;
			xlnx,vid-phy-tx-axi4s-ch-tdata-width = <0x14>;
			xlnx,vid-phy-tx-axi4s-ch-tuser-width = <0x1>;
			xlnx,viper-reg = "false";
		};

I have tried to instantiate and constrain the Video PHY Controller in my FPGA design using example design that comes with the HDMI TX core.

The issue is that the default configurations for the Video PHY core are not consistent with those listed here for the Linux driver.

https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18841797/Xilinx+Phy+VideoPhy+Driver

I cannot seem to get my hardware to build when I set GT: Starting Channel Location to X0Y4 as suggested in the Wiki. I also did not include and Rx Protocol Selection

videophy.png

Has anyone been able to get this thing to work with the DRM KMS Linux drivers? Do I need to enable and constrain the Receiver to generate a parsable device tree node? Am I allowed any deviation from the hardware configurations in the Wiki? Is the driver compatible with PetaLinux 2018.2 and Video PHY Controller IP Version 2.2?

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Xilinx Employee
Xilinx Employee
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Registered: ‎08-02-2007

Re: Linux Video PHY Driver Fail to Parse Device Tree

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Hi @johnfrye11 

Please refer to the device tree from our FrameBuffer example design : https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/33128528/HDMI+FrameBuffer+Example+Design+2018.3

As you have included pl.dtsi in your system_user,dtsi, so you don't need to define Video PHY node again, as it's already defined in pl.dtsi.

Let's have a close look at the Video PHY clock connection. In the example below, AXI Lite clock of Video PHY is driven by &clk 71.

vid_phy_controller: vid_phy_controller@80050000 {
compatible = "xlnx,vid-phy-controller-2.2";
interrupt-parent = <&gic>;
interrupts = <0 89 4>;
reg = <0x0 0x80050000 0x0 0x10000>;
clocks = <&axi_lite_clk>, <&si570_2>;
clock-names = "axi-lite", "dru-clk";

 

axi_lite_clk: axi_lite_clk {
compatible = "fixed-factor-clock";
clocks = <&clk 71>;
#clock-cells = <0>;
clock-div = <1>;
clock-mult = <1>;
};

 

In the Framebuffer example design, AXI Lite Clock is driven from PL Clock of Zynq Ultrascale Processor. This part of clock is generated by DTG automatically, so you can find node definition in

apu\petalinux_bsp\components\plnx_workspace\device-tree\device-tree\zynqmp-clk-ccf.dtsi

fclk0: fclk0 {
status = "disabled";
compatible = "xlnx,fclk";
clocks = <&clk 71>;
};

fclk1: fclk1 {
status = "disabled";
compatible = "xlnx,fclk";
clocks = <&clk 72>;
};

fclk2: fclk2 {
status = "disabled";
compatible = "xlnx,fclk";
clocks = <&clk 73>;
};

fclk3: fclk3 {
status = "disabled";
compatible = "xlnx,fclk";
clocks = <&clk 74>;
};

I notice in your hdf, the AXi clock is driven from PL0 Clock too, so you can keep the same for axi_lite_clk 

DRU clock is generated from on board Si570. Please note it doesn't care the clock is from which quad.

The Si570 clock node is defined in apu\petalinux_bsp\project-spec\meta-user\recipes-bsp\device-tree\files\zcu102\zcu102-rev1.0.dtsi

 

i2c@3 { /* i2c mw 74 0 8 */
#address-cells = <1>;
#size-cells = <0>;
reg = <3>;
si570_2: clock-generator3@5d { /* USER MGT SI570 - u56 */
#clock-cells = <0>;
compatible = "silabs,si570";
reg = <0x5d>;
temperature-stability = <50>; 
factory-fout = <156250000>;
clock-frequency = <148500000>;
};

 

I2S node is defined in system_user.dtsi : 

---

#include "zcu102/zcu102-rev1.0.dtsi"
#include "zcu102/pcw.dtsi"
/ {
aliases {
ethernet0 = &gem3;
i2c0 = &zynq_us_ss_0_fmch_axi_iic;
i2c1 = &i2c0;
i2c2 = &i2c1;
serial0 = &uart0;
serial1 = &uart1;
spi0 = &qspi;

 


};
memory {
device_type = "memory";
reg = <0x0 0x0 0x0 0x7ff00000>, <0x00000008 0x00000000 0x0 0x80000000>;
};
};
#include "zcu102/system-conf.dtsi"

/* Includes */
#include "hdmi/pl.dtsi"

----

So you only need to figure out the clock node that is defined for ZCU104 on board clock, and use the name of node to replace si570_2 in the pl.dtsi for dru clock connection.

12 Replies
Explorer
Explorer
1,277 Views
Registered: ‎10-18-2017

Re: Linux Video PHY Driver Fail to Parse Device Tree

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So I started reading through the driver here

https://github.com/Xilinx/hdmi-modules/blob/master/hdmi/phy-vphy.c

On the probe there is a list of properties that must be present in the device tree. If these properties are not present, it prints the error I am seeing that exits the probe with an error

These are the properties

 

xlnx,transceiver-type
xlnx,tx-buffer-bypass
xlnx,input-pixels-per-clock
xlnx,nidru
xlnx,nidru-refclk-sel
xlnx,rx-no-of-channels
xlnx,tx-no-of-channels
xlnx,rx-protocol
xlnx,tx-protocol
xlnx,rx-refclk-sel
xlnx,tx-refclk-sel
xlnx,rx-pll-selection
xlnx,tx-pll-selection
xlnx,hdmi-fast-switch
xlnx,transceiver-width
xlnx,err-irq-en

It looks like I am missing

 

xlnx,transceiver-type
xlnx,tx-buffer-bypass
xlnx,transceiver-width 

Why does the driver require these properties and why is the DTG not parsing them from the HDF?

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Xilinx Employee
Xilinx Employee
1,197 Views
Registered: ‎08-02-2007

Re: Linux Video PHY Driver Fail to Parse Device Tree

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@johnfrye11 

If you take a look at Required Properties section :

https://github.com/Xilinx/hdmi-modules/blob/master/Documentation/devicetree/bindings/xlnx%2Cvphy.txt

Following properties are required for sure :

 - xlnx,transceiver-type: GT type. Must be set per GT device used
 - xlnx,tx-buffer-bypass: Flag to indicate buffer bypass logic availability
 - xlnx,transceiver-width: Defines 4 Byte or 2 Byte mode

 

It seems there is issue when device tree file is generated from hdf. I don't think we have tested TX only yet. Can you share hdf file, I will check if it's really an issue.

 

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Explorer
Explorer
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Registered: ‎10-18-2017

Re: Linux Video PHY Driver Fail to Parse Device Tree

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@xud I have reconfigured the hardware to include both TX and RX with the hope to generate all of the properties the driver requires.

Currently though, the node looks like this

vid_phy_controller_0: vid_phy_controller@80060000 {
                        clock-names = "mgtrefclk0_pad_p_in", "mgtrefclk0_pad_n_in", "mgtrefclk1_pad_p_in", "mgtrefclk1_pad_n_in", "gtnorthrefclk1_in", "gtnorthrefclk1_odiv2_in", "vid_phy_tx_axi4s_aclk", "vid_phy_rx_axi4s_aclk", "vid_phy_sb_aclk", "vid_phy_axi4lite_aclk", "drpclk";
                        clocks = <&misc_clk_2>, <&misc_clk_2>, <&misc_clk_2>, <&misc_clk_2>, <&misc_clk_2>, <&misc_clk_2>, <&misc_clk_0>, <&misc_clk_0>, <&clk 71>, <&clk 71>, <&clk 71>;
                        compatible = "xlnx,vid-phy-controller-2.2", "xlnx,vid-phy-controller-2.1";
                        interrupt-names = "irq";
                        interrupt-parent = <&gic>;
                        interrupts = <0 89 4>;
                        reg = <0x0 0x80060000 0x0 0x10000>;
                        xlnx,hdmi-fast-switch = <1>;
                        xlnx,input-pixels-per-clock = <2>;
                        xlnx,nidru = <1>;
                        xlnx,nidru-refclk-sel = <3>;
                        xlnx,rx-no-of-channels = <3>;
                        xlnx,rx-pll-selection = <0>;
                        xlnx,rx-protocol = <1>;
                        xlnx,rx-refclk-sel = <1>;
                        xlnx,transceiver-type = <5>;
                        xlnx,transceiver-width = <2>;
                        xlnx,tx-buffer-bypass = <1>;
                        xlnx,tx-no-of-channels = <3>;
                        xlnx,tx-pll-selection = <6>;
                        xlnx,tx-protocol = <1>;
                        xlnx,tx-refclk-sel = <0>;
                        vphy_lane0: vphy_lane@0 {
                                #phy-cells = <4>;
                        };
                        vphy_lane1: vphy_lane@1 {
                                #phy-cells = <4>;
                        };
                        vphy_lane2: vphy_lane@2 {
                                #phy-cells = <4>;
                        };
                        vphy_lane3: vphy_lane@3 {
                                #phy-cells = <4>;
                        };
                };

The example from the 2018.3 txt example file looks like this

vid_phy_controller_0: vid_phy_controller@a0090000 {
		compatible = "xlnx,vid-phy-controller-2.2";
		reg = <0x0 0xa0090000 0x0 0x10000>;
		interrupts = <0 92 4>;
		interrupt-parent = <&gic>;
		clocks = <&vid_s_axi_clk>, <&si570_2>;
		clock-names = "axi-lite", "dru-clk";

		xlnx,input-pixels-per-clock = <0x2>;
		xlnx,nidru = <0x1>;
		xlnx,nidru-refclk-sel = <0x4>;
		xlnx,rx-no-of-channels = <0x3>;
		xlnx,rx-pll-selection = <0x0>;
		xlnx,rx-protocol = <0x1>;
		xlnx,rx-refclk-sel = <0x1>;
		xlnx,tx-no-of-channels = <0x3>;
		xlnx,tx-pll-selection = <0x6>;
		xlnx,tx-protocol = <0x1>;
		xlnx,tx-refclk-sel = <0x0>;
		xlnx,hdmi-fast-switch = <0x1>;
		xlnx,transceiver-type = <0x5>;
		xlnx,tx-buffer-bypass = <0x1>;
		xlnx,transceiver-width = <0x2>;

		vphy_lane0: vphy_lane@0 {
			#phy-cells = <4>;
		};
		vphy_lane1: vphy_lane@1 {
			#phy-cells = <4>;
		};
		vphy_lane2: vphy_lane@2 {
			#phy-cells = <4>;
		};
		vphy_lane3: vphy_lane@3 {
			#phy-cells = <4>;
		};
	};

I am not sure why the clock and clock-names fields do not look more like the example. Note that this was the output from the DTG in components/plnx_workspace/device-tree/device-tree/pl.dtsi

Driver failing on probe with message

[ 4.599859] xilinx-vphy 80060000.vid_phy_controller: failed to get the axi lite clk.

from 

https://github.com/Xilinx/hdmi-modules/blob/309e4f340d36d9179bce2d86ff17514b418d9885/hdmi/phy-vphy.c#L493

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Explorer
Explorer
1,116 Views
Registered: ‎10-18-2017

Re: Linux Video PHY Driver Fail to Parse Device Tree

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Update:

Did a little more digging and found in the documentation here https://github.com/Xilinx/hdmi-modules/blob/master/Documentation/devicetree/bindings/xlnx%2Cvphy.txt that

Required Properties:
 - compatible: Should be "xlnx,vid-phy-controller-2.2".
 - reg: Base address and size of the IP core.
 - interrupts: Interrupt number.
 - interrupts-parent: phandle for interrupt controller.

 - clocks: phandle of all the clocks required by IP are listed here.
 - clock-names: names of all the clocks required by IP are listed here.
          NOTE: Auto generated DT is providing all the clock names and handles
          reuired by the IP.
          NOTE: The identification string, "vid_phy_axi4lite_aclk", is always
          required.
          NOTE: The identification string "dru-clk" is always required if
          NI DRU (nidru parameter) is selected for phy. This needs to be
          explicitly added in the list of clock-names and its phandle in clocks
          as its derived by external clock.

 - xlnx,input-pixels-per-clock: IP configuration for samples/clk (1, 2, 4)
         Note: Only 2 is supported at this time
 - xlnx,nidru: flag to indicate if DRU is present
 - xlnx,nidru-refclk-sel: DRU clock selector
 - xlnx,rx-no-of-channels: Required Rx channels for registered protocol
 - xlnx,rx-pll-selection: Rx pll selector
 - xlnx,rx-protocol: 1=HDMI, 0=DP (Note: Only HDMI is supported at this time)
 - xlnx,rx-refclk-sel: Reference Rx clock selector
 - xlnx,tx-no-of-channels: Required Rx channels for registered protocol
 - xlnx,tx-pll-selection = Tx pll selector
 - xlnx,tx-protocol: 1=HDMI, 0=DP (Note: Only HDMI is supported at this time)
 - xlnx,tx-refclk-sel: Reference Rx clock selector
 - xlnx,hdmi-fast-switch: Flag to indicate fast switching logic availability
 - xlnx,transceiver-type: GT type. Must be set per GT device used
 - xlnx,tx-buffer-bypass: Flag to indicate buffer bypass logic availability
 - xlnx,transceiver-width: Defines 4 Byte or 2 Byte mode
                      (Note: Only 2 byte is supported at this time)

My device tree has all the proper clock names according to the UDPATED documentation. Here is what the updated documentation has 

vid_phy_controller: vid_phy_controller@80120000 {
		compatible = "xlnx,vid-phy-controller-2.2";
		reg = <0x0 0xa0090000 0x0 0x10000>;
		interrupts = <0 92 4>;
		interrupt-parent = <&gic>;
		clock-names = "mgtrefclk0_pad_p_in", "mgtrefclk0_pad_n_in", "mgtrefclk1_pad_p_in", "mgtrefclk1_pad_n_in", "gtsouthrefclk0_in", "gtsouthrefclk0_odiv2_in", "vid_phy_tx_axi4s_aclk", "vid_phy_rx_axi4s_aclk", "vid_phy_sb_aclk", "vid_phy_axi4lite_aclk", "drpclk", "dru-clk";
		clocks = <&misc_clk_0>, <&misc_clk_0>, <&misc_clk_0>, <&misc_clk_0>, <&misc_clk_3>, <&misc_clk_3>, <&misc_clk_1>, <&misc_clk_1>, <&zynqmp_clk 71>, <&zynqmp_clk 71>, <&zynqmp_clk 71>, <&si570_2>;

		xlnx,input-pixels-per-clock = <0x2>;
		xlnx,nidru = <0x1>;
		xlnx,nidru-refclk-sel = <0x4>;
		xlnx,rx-no-of-channels = <0x3>;
		xlnx,rx-pll-selection = <0x0>;
		xlnx,rx-protocol = <0x1>;
		xlnx,rx-refclk-sel = <0x1>;
		xlnx,tx-no-of-channels = <0x3>;
		xlnx,tx-pll-selection = <0x6>;
		xlnx,tx-protocol = <0x1>;
		xlnx,tx-refclk-sel = <0x0>;
		xlnx,hdmi-fast-switch = <0x1>;
		xlnx,transceiver-type = <0x5>;
		xlnx,tx-buffer-bypass = <0x1>;
		xlnx,transceiver-width = <0x2>;

		vphy_lane0: vphy_lane@0 {
			#phy-cells = <4>;
		};
		vphy_lane1: vphy_lane@1 {
			#phy-cells = <4>;
		};
		vphy_lane2: vphy_lane@2 {
			#phy-cells = <4>;
		};
		vphy_lane3: vphy_lane@3 {
			#phy-cells = <4>;
		};
	};

According to the Github, the files (both documentation and drivers) were updated three days ago as of 4/11/19. Perhaps I will rebuild with same hardware and new software and try this all over again. I expect it will then work, since last post the device tree property requirements and source code were different.

Could a Xilinx rep confirm this?

Thanks.

Xilinx Employee
Xilinx Employee
1,100 Views
Registered: ‎08-02-2007

Re: Linux Video PHY Driver Fail to Parse Device Tree

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Hi @johnfrye11 

The best way is to check the device tree from HDMI Framebuffer example design 2018.3, which is up-to-date. You need to ensure the property value and address matches the one in your design :

  vid_phy_controller: vid_phy_controller@80050000 {
   compatible = "xlnx,vid-phy-controller-2.2";
   interrupt-parent = <&gic>;
   interrupts = <0 89 4>;
   reg = <0x0 0x80050000 0x0 0x10000>;
   clocks = <&axi_lite_clk>, <&si570_2>;
   clock-names = "axi-lite", "dru-clk";
   xlnx,hdmi-fast-switch = <0x1>;
   xlnx,input-pixels-per-clock = <0x2>;
   xlnx,nidru = <0x1>;
   xlnx,nidru-refclk-sel = <0x4>;
   xlnx,rx-no-of-channels = <0x3>;
   xlnx,rx-pll-selection = <0x0>;
   xlnx,rx-protocol = <0x1>;
   xlnx,rx-refclk-sel = <0x1>;
   xlnx,tx-no-of-channels = <0x3>;
   xlnx,tx-pll-selection = <0x6>;
   xlnx,tx-protocol = <0x1>;
   xlnx,tx-refclk-sel = <0x0>;
   xlnx,transceiver-type = <0x5>;
   xlnx,tx-buffer-bypass = <0x1>;
   xlnx,transceiver-width = <0x2>;
   vphy_lane0: vphy_lane@0 {
    #phy-cells = <4>;
   };
   vphy_lane1: vphy_lane@1 {
    #phy-cells = <4>;
   };
   vphy_lane2: vphy_lane@2 {
    #phy-cells = <4>;
   };
   vphy_lane3: vphy_lane@3 {
    #phy-cells = <4>;
   };
  };
 };

 

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Xilinx Employee
Xilinx Employee
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Registered: ‎08-02-2007

Re: Linux Video PHY Driver Fail to Parse Device Tree

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Hi @johnfrye11 

I have confirmed the Video PHY Device tree needs to be manually added in 2018.3. When you are using device tree example, you need to modify the address(based on assigned address in IPI), and clock connection.

Currently we only have tested it with ZCU102 and ZCU106 board, I will need to find an example for ZCU104, and check what clock connection should be.

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Explorer
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Re: Linux Video PHY Driver Fail to Parse Device Tree

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@xud I think I can parse out what the axi-lite and dru-clk should be. It seems based on reVision that the "axi-lite" should be pl_clk0 or whatever the associated phandle is, in my case it is one of the "misc_clk" nodes. I think the "dru-clk" is the clock connected to gtnorthrefclk1_in, which is established using an external input and Utility Buffer IPs. Please correct me if I am wrong.

At this point I am struggling to actually write the device tree with the correct syntax. PetaLinux is telling me that there are syntax errors in my device tree. Here is system-user.dtsi

/include/ "system-conf.dtsi"
/include/ "pl.dtsi"
/ {
	&vid_phy_controller_0 {
			clock-names = "mgtrefclk0_pad_p_in", "mgtrefclk0_pad_n_in", "mgtrefclk1_pad_p_in", "mgtrefclk1_pad_n_in", "gtnorthrefclk1_in", "gtnorthrefclk1_odiv2_in", "vid_phy_tx_axi4s_aclk", "vid_phy_rx_axi4s_aclk", "vid_phy_sb_aclk", "vid_phy_axi4lite_aclk", "drpclk", "axi-lite", "dru-clk";
			clocks = <&misc_clk_2>, <&misc_clk_2>, <&misc_clk_2>, <&misc_clk_2>, <&misc_clk_2>, <&misc_clk_2>, <&misc_clk_0>, <&misc_clk_0>, <&clk 71>, <&clk 71>, <&clk 71>, <&clk 71>, <&misc_clk_2>;
	};
			
};

where there is a node in pl.dtsi under amba_pl called 

vid_phy_controller_0: vid_phy_controller@80060000 {
			clock-names = "mgtrefclk0_pad_p_in", "mgtrefclk0_pad_n_in", "mgtrefclk1_pad_p_in", "mgtrefclk1_pad_n_in", "gtnorthrefclk1_in", "gtnorthrefclk1_odiv2_in", "vid_phy_tx_axi4s_aclk", "vid_phy_rx_axi4s_aclk", "vid_phy_sb_aclk", "vid_phy_axi4lite_aclk", "drpclk";
			clocks = <&misc_clk_2>, <&misc_clk_2>, <&misc_clk_2>, <&misc_clk_2>, <&misc_clk_2>, <&misc_clk_2>, <&misc_clk_0>, <&misc_clk_0>, <&clk 71>, <&clk 71>, <&clk 71>;
			compatible = "xlnx,vid-phy-controller-2.2", "xlnx,vid-phy-controller-2.1";
			interrupt-names = "irq";
			interrupt-parent = <&gic>;
			interrupts = <0 89 4>;
			reg = <0x0 0x80060000 0x0 0x10000>;
			xlnx,hdmi-fast-switch = <1>;
			xlnx,input-pixels-per-clock = <2>;
			xlnx,nidru = <1>;
			xlnx,nidru-refclk-sel = <3>;
			xlnx,rx-no-of-channels = <3>;
			xlnx,rx-pll-selection = <0>;
			xlnx,rx-protocol = <1>;
			xlnx,rx-refclk-sel = <1>;
			xlnx,transceiver-type = <5>;
			xlnx,transceiver-width = <2>;
			xlnx,tx-buffer-bypass = <1>;
			xlnx,tx-no-of-channels = <3>;
			xlnx,tx-pll-selection = <6>;
			xlnx,tx-protocol = <1>;
			xlnx,tx-refclk-sel = <0>;
			vphy_lane0: vphy_lane@0 {
				#phy-cells = <4>;
			};
			vphy_lane1: vphy_lane@1 {
				#phy-cells = <4>;
			};
			vphy_lane2: vphy_lane@2 {
				#phy-cells = <4>;
			};
			vphy_lane3: vphy_lane@3 {
				#phy-cells = <4>;
			};
		};

The error the tool is throwing is this

Error: <root>/build/tmp/work/plnx_zynqmp-xilinx-linux/device-tree/xilinx+gitAUTOINC+b7466bbeee-r0/system-user.dtsi:4.2-23 syntax error. I am not exactly a device tree expert so I am wondering what is wrong on the fourth line and why there would be an error.

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Xilinx Employee
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Registered: ‎08-02-2007

Re: Linux Video PHY Driver Fail to Parse Device Tree

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Hi @johnfrye11 

Please refer to the device tree from our FrameBuffer example design : https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/33128528/HDMI+FrameBuffer+Example+Design+2018.3

As you have included pl.dtsi in your system_user,dtsi, so you don't need to define Video PHY node again, as it's already defined in pl.dtsi.

Let's have a close look at the Video PHY clock connection. In the example below, AXI Lite clock of Video PHY is driven by &clk 71.

vid_phy_controller: vid_phy_controller@80050000 {
compatible = "xlnx,vid-phy-controller-2.2";
interrupt-parent = <&gic>;
interrupts = <0 89 4>;
reg = <0x0 0x80050000 0x0 0x10000>;
clocks = <&axi_lite_clk>, <&si570_2>;
clock-names = "axi-lite", "dru-clk";

 

axi_lite_clk: axi_lite_clk {
compatible = "fixed-factor-clock";
clocks = <&clk 71>;
#clock-cells = <0>;
clock-div = <1>;
clock-mult = <1>;
};

 

In the Framebuffer example design, AXI Lite Clock is driven from PL Clock of Zynq Ultrascale Processor. This part of clock is generated by DTG automatically, so you can find node definition in

apu\petalinux_bsp\components\plnx_workspace\device-tree\device-tree\zynqmp-clk-ccf.dtsi

fclk0: fclk0 {
status = "disabled";
compatible = "xlnx,fclk";
clocks = <&clk 71>;
};

fclk1: fclk1 {
status = "disabled";
compatible = "xlnx,fclk";
clocks = <&clk 72>;
};

fclk2: fclk2 {
status = "disabled";
compatible = "xlnx,fclk";
clocks = <&clk 73>;
};

fclk3: fclk3 {
status = "disabled";
compatible = "xlnx,fclk";
clocks = <&clk 74>;
};

I notice in your hdf, the AXi clock is driven from PL0 Clock too, so you can keep the same for axi_lite_clk 

DRU clock is generated from on board Si570. Please note it doesn't care the clock is from which quad.

The Si570 clock node is defined in apu\petalinux_bsp\project-spec\meta-user\recipes-bsp\device-tree\files\zcu102\zcu102-rev1.0.dtsi

 

i2c@3 { /* i2c mw 74 0 8 */
#address-cells = <1>;
#size-cells = <0>;
reg = <3>;
si570_2: clock-generator3@5d { /* USER MGT SI570 - u56 */
#clock-cells = <0>;
compatible = "silabs,si570";
reg = <0x5d>;
temperature-stability = <50>; 
factory-fout = <156250000>;
clock-frequency = <148500000>;
};

 

I2S node is defined in system_user.dtsi : 

---

#include "zcu102/zcu102-rev1.0.dtsi"
#include "zcu102/pcw.dtsi"
/ {
aliases {
ethernet0 = &gem3;
i2c0 = &zynq_us_ss_0_fmch_axi_iic;
i2c1 = &i2c0;
i2c2 = &i2c1;
serial0 = &uart0;
serial1 = &uart1;
spi0 = &qspi;

 


};
memory {
device_type = "memory";
reg = <0x0 0x0 0x0 0x7ff00000>, <0x00000008 0x00000000 0x0 0x80000000>;
};
};
#include "zcu102/system-conf.dtsi"

/* Includes */
#include "hdmi/pl.dtsi"

----

So you only need to figure out the clock node that is defined for ZCU104 on board clock, and use the name of node to replace si570_2 in the pl.dtsi for dru clock connection.

Xilinx Employee
Xilinx Employee
870 Views
Registered: ‎08-02-2007

Re: Linux Video PHY Driver Fail to Parse Device Tree

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@johnfrye11 

I have confirmed the clocks/clock-names below in vphy device tree node is supposed to be used for next release of our tool. The only clock you need to add manually is dru-clk. vid_phy_axi4lite_aclk will be auto-generated by DTG. 

		clock-names = "mgtrefclk0_pad_p_in", "mgtrefclk0_pad_n_in", "mgtrefclk1_pad_p_in", "mgtrefclk1_pad_n_in", "gtsouthrefclk0_in", "gtsouthrefclk0_odiv2_in", "vid_phy_tx_axi4s_aclk", "vid_phy_rx_axi4s_aclk", "vid_phy_sb_aclk", "vid_phy_axi4lite_aclk", "drpclk", "dru-clk";
		clocks = <&misc_clk_0>, <&misc_clk_0>, <&misc_clk_0>, <&misc_clk_0>, <&misc_clk_3>, <&misc_clk_3>, <&misc_clk_1>, <&misc_clk_1>, <&zynqmp_clk 71>, <&zynqmp_clk 71>, <&zynqmp_clk 71>, <&si570_2>;

 If you are working on 2018.3, please use the clock/clock-names as below : 

clocks = <&axi_lite_clk>, <&si570_2>;
clock-names = "axi-lite", "dru-clk";

Explorer
Explorer
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Registered: ‎10-18-2017

Re: Linux Video PHY Driver Fail to Parse Device Tree

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That looks good and is similar to what I have been seeing going through reVision 2018,3 DTG's. I will look at that reference design and add those changes and test the drivers. 

I will probably need to open other questions about device tree configuration as I try to get the other IP drivers within the Xilinx DRM-KMS HDMI-Tx Driver hardware pipeline to initialize. 

For this pipeline, it appears I need a FrameBuffer Read -> HDMI TX SS -> Video PHY (Constrained) to board as well as proper I2C connections for configuration negotiation, which means all those devices will need to probe successfully, correct?

Also as one final question, if all of these node initialize properly, I should expect to see a file /dev/dri/xlnx or /dev/dri/card0 that I can use to create DRM dumb buffers, or will I have to perform a DMA transaction through the framebuffer?

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Re: Linux Video PHY Driver Fail to Parse Device Tree

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@johnfrye11 

Firstly you should be able to figure it out by looking at the termanial log. For example :

[    9.043496] xilinx-frmbuf a0010000.v_frmbuf_wr: Xilinx AXI frmbuf DMA_DEV_TO_MEM
[    9.050971] xilinx-frmbuf a0010000.v_frmbuf_wr: Xilinx AXI FrameBuffer Engine Driver Probed!!
[    9.059616] xilinx-frmbuf a0040000.v_frmbuf_rd: Xilinx AXI frmbuf DMA_MEM_TO_DEV
[    9.067071] xilinx-frmbuf a0040000.v_frmbuf_rd: Xilinx AXI FrameBuffer Engine Driver Probed!!

Then you should be able to see all the related PL node under /sys/devices/platform/amba_pl@0/

To check if HDMI TX is configured correctly, you can use cat /sys/devices/platform/amba_pl@0/a0020000.v_hdmi_tx_ss/hdmi_info.

hdmi_tx.JPG

Note the path might be different depends on your project. You can always use ls to get the correct name.

 

 

Moderator
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Registered: ‎11-09-2015

Re: Linux Video PHY Driver Fail to Parse Device Tree

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HI @johnfrye11 ,

Do you have any update on this? Were you able to have everythin

If your question is answered or your issue is solved, please kindly mark the response which helped as solution (click on "Accept as solution" button below the reply)

If this is not solved/answered, please reply in the topic giving more information on your current status.

Thanks and Regards,

g working?

 


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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