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Contributor
Contributor
199 Views
Registered: ‎12-12-2018

MIPI Bitslice Control Delay

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Hello,

I was wondering if we could have more information about how delay tuning is done on the MIPI block with Ultrascale+ devices when using the MIPI RX subsystem.

  1. Is this done automatically by the block?
  2. Do we have to add any additional constraints with known delays from our PCB boards?
  3. How much delay can be compensated?
  4. Can both positive and negative delays relative to the clock be compensated?

Thanks!

Mark

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Xilinx Employee
Xilinx Employee
91 Views
Registered: ‎03-30-2016

Re: MIPI Bitslice Control Delay

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Hello Mark

>Theoretically, there should be a way to specify the boot up settings for the BITSLICE CONTROL on a per interface setting correct?

User will not be able to set custom delay using taps in the bitslice control.
MIPI D-PHY IP will "train" each line automatically every LP --> HS transition, so each data lane will be sampled correctly.

Thanks & regards
Leo

8 Replies
Xilinx Employee
Xilinx Employee
180 Views
Registered: ‎03-30-2016

Re: MIPI Bitslice Control Delay

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Hello Mark @markramona 

>Is this done automatically by the block?

Yes.

>Do we have to add any additional constraints with known delays from our PCB boards?

No, not necessary.

>How much delay can be compensated?

If the delay is within range mentioned by the spec, it can be compensated and already tested.

Note :
Delay between clock and any data lane should be less than UI/50 for all line-rates.

XF_MIPI_DATA_CLOCK_DELAY.jpg

 

Please also ensure that RX Setup/Hold requirement is not violated.

XF_MIPI_DPHY_RX_SETUP_HOLD.jpg

>Can both positive and negative delays relative to the clock be compensated?

Yes, both can be compensated.

Thanks & regards
Leo

Contributor
Contributor
167 Views
Registered: ‎12-12-2018

Re: MIPI Bitslice Control Delay

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Hi @karnanl

That is super helpful!

Thanks!

What is the document that you referred to? I would like to take some to read it in depth.

We might have up to UI/30 of static delay in our system. Do you have a reference on how we can designs constraints that take this amount of delay into account?

Thanks!

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Xilinx Employee
Xilinx Employee
156 Views
Registered: ‎03-30-2016

Re: MIPI Bitslice Control Delay

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Hello Mark @markramona 

> What is the document that you referred to? I would like to take some to read it in depth.

This is taken from mipi_D-PHY_specification_v1-1.pdf
-- You can download this document from (https://members.mipi.org/wg/All-Members/document/folder/8354)
   You can download for free, if you company is mipi.org member.

>We might have up to UI/30 of static delay in our system.
>Do you have a reference on how we can designs constraints that take this amount of delay into account?

Hmm, pardon me but I do not have the answer.

1. I would suggest you to fix your board to follow MIPI spec.
2. I do see that some customer boards working without any issue with static delay larger than UI/50. (~20ps delay for 1500Mbps line-rate), but we cannot guarantee that the same number will achievable on your board.

Thanks & regards
Leo

Contributor
Contributor
136 Views
Registered: ‎12-12-2018

Re: MIPI Bitslice Control Delay

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Hi Leo,

Thank you for the fast response.
That all makes sense. We will keep it in mind for future iterations of our design.

Theoretically, there should be a way to specify the boot up settings for the BITSLICE CONTROL on a per interface setting correct?
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Moderator
Moderator
111 Views
Registered: ‎11-21-2018

Re: MIPI Bitslice Control Delay

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Hi @markramona,

If your question is answered or your issue is solved, please kindly mark the response which helped as solution (click on "Accept as solution" button below the reply)
 
If this is not solved/answered, please reply in the topic giving more information on your current status.
 
Thanks and Regards,
Aoife
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
Contributor
Contributor
99 Views
Registered: ‎12-12-2018

Re: MIPI Bitslice Control Delay

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It is hard to say if the question has been "answered" or not.

I would say the question has been half answered.

Yes we were able to define some bounds under which the MIPI signal would be correctly captured by the FPGA using the IP, but I'm still unclear about how to customize the the delay using the taps in the bitslice control is still unclear.

Xilinx Employee
Xilinx Employee
92 Views
Registered: ‎03-30-2016

Re: MIPI Bitslice Control Delay

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Hello Mark

>Theoretically, there should be a way to specify the boot up settings for the BITSLICE CONTROL on a per interface setting correct?

User will not be able to set custom delay using taps in the bitslice control.
MIPI D-PHY IP will "train" each line automatically every LP --> HS transition, so each data lane will be sampled correctly.

Thanks & regards
Leo

Contributor
Contributor
79 Views
Registered: ‎12-12-2018

Re: MIPI Bitslice Control Delay

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Awesome, thanks, for the quick response.

 

Taking this into account it seems that while the MIPI spec requires lines to be matched to UI/50, there should be some slack due to the training that is possible on every LP -> HS transitions.