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Contributor
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Registered: ‎05-11-2018

MIPI CSI-2, D-phy Tx - No Video Output, No mipi_out_clk_lp

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In simulation I don't get any mipi_out_clk_lp and the hs and lp output data are mostly stuck at 0xF.  I'm using a Spartan 7 (xc7s25csga324-2).  The MIPI core has the following settings: Native input video interface with 4 CSI lanes, 2 input pixels per beat, 4096 line buffer depth, CRC generation logic, enabled active lanes, 594Mbps, include shared logic in core.

 

The input is 1080p60, YUV 4:2:2 8-bits .

 

The interrupt status register of the CSI-2 core indicates that there are no issues.  The core indicates that it is ready.

 

 I've attached simulation results showing several frames of video.

 

Any suggestions?

 

Thanks,

mipi Tx core 1.png
mipi Tx core 2.png
mipi Tx core 3.png
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Re: MIPI CSI-2, D-phy Tx - No Video Output, No mipi_out_clk_lp

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Hello @sparky989

Thank you for sharing your update.

 

If you are sending video data in HS mode only, you will never see lp_clk toggling.

I think you are doing good.

 

If you are sending data in Low power mode (escape mode) then you will see lp_clk toggling.

Do you use Escape mode ??

 

BTW, I am interested to see the HW waveform.

 

Best regards

Leo

 

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Re: MIPI CSI-2, D-phy Tx - No Video Output, No mipi_out_clk_lp

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Hello @sparky989

I am trying to understand the waveform you shared......

From my understanding I believe you do not set the input signal correctly.

 

1. vid_hsync is toggling while vid_vsync=high. This is not correct (please see PG260 Figure B-3)

2. You set the Data type as 0x2E (=Reserved). This is not correct (Please check MIPI CSI-2 specification)

    -- If you want to send YUV422 8 bit , data type 0x1E is the correct setting.

3. what is the clock freq. of your s_axis_aclk ?

4. Could you share your interrupt status register ? ( is Pixel Data under-run occurred ? Is Line buffer full asserted ?)

 

Thanks & regards

Leo

 

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Re: MIPI CSI-2, D-phy Tx - No Video Output, No mipi_out_clk_lp

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Hello @karnanl,

 

You're right that the data ID was 0x2e when we meant it to be 0x1e for CSI-2 YUV, 4:2:2 8-bit.  I try correcting that.

 

 

Both VSYNC and HSYNC are toggling in the waveforms I attached.  VSYNC is toggling much more slowly and is low most of the type and high during vertical sync as in PG260 Figure B-3.

 

Here is some more information.

 

I've also checked all the debug steps mentioned in PG260 and they all look OK with the possible exception of not making HSYNC narrower than VIDENABLE horizontally by the horizontal front porch and back porch.

 

Real hardware is acting similarly to simulation.  The interrupt status register in simulation is always all 0s so there are no errors.  My hardware constantly reads it in a loop so there should be no data underrun.  The pixel data is encoded per table 2-5 for dual pixel per beat for YUV244 8-bit in pg260  as follows for the 84-bit (14*3*pixel-mode=2) mipi_din[83:0]:
mipi_din[55:48] = V0[7:0] (even chrome byte), mipi_din[41:34] = Y1[7:0] (even luma byte), mipi_din[27:20] = U0[7:0] (odd chroma byte), mipi_din[13:6] = Y0[7:0] (odd luma byte) where in the Y and V bit 7 is the MSbit and bit 0 is the LSbit.  All other bits of mipi_din[83:0] are 0b0. Also the odd luma byte occurs before the even luma byte.

 

The D-phy interface isn't enabled.  For the CSI-2, the initialization logic is as follows: 

1. hold the mipi_reset asserted low for 63 of the s_axi_aclk periods and then is deasserted high.  this duration is longer than the minimum requirement of 40 cycles of 200MHz = 200ns.

 

2. Continue to read the MIPI_CORE_CONFIG_REGISTER_ADDRESS until bit 2 (Core controller ready) is a '1'.

 

3. Write to the MIPI_CORE_PROTOCOL_CONFIG_REGISTER_ADDRESS a value of x"00000003" so active lanes = 4 MIPI lanes.

 

4. Enable the core by writing 0x01 to the MIPI_CORE_CONFIG_REGISTER_ADDRESS.

 

5. Enable  the Video Enable input to the core and sit in a loop continuously reading the MIPI_CORE_INTERRUPT_STATUS_REGISTER_ADDRESS.  

 

The DPHY clock is 200MHz.

s_axis_aclk is 94.5MHz

 

mipi_video_if_mipi_vid_di[5:0]     = "101110" = 0x2e - you're write it was meant to be 0x1e which I thought was the data id of a long packet for YUV 422 8-bit of 0x1e.

mipi_video_if_mipi_vid_vc[1:0]    = "00" (virtual channel 0) - we aren't using MIPI virtual channels.

mipi_video_if_mipi_vid_wc[15:0] =  0x0f00 (= 0d3840 byte for 1080p 4:2:2 1920 active horizontal pixels x 16 bits/pixel = 3840 active bytes/line)

 

 

 

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Re: MIPI CSI-2, D-phy Tx - No Video Output, No mipi_out_clk_lp

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@karnanl,

 

Here is the 17ms (1 frame) simulation result after I corrected the ID to 0x1e.

 

There still is no mipi lp clock.

 

I've added zoomed out (17ms waveform width) for all MIPI signals and a zoomed in view of a horizontal line and then of the clocks.

 

 

sim after correct 0x1e-1.png
sim after correct 0x1e-2.png
sim after correct 0x1e-3.png
sim after correct 0x1e - zoom in on horizontal line.png
sim after correct 0x1e-5 zoom in on clocks.png
Xilinx Employee
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Re: MIPI CSI-2, D-phy Tx - No Video Output, No mipi_out_clk_lp

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Hello @sparky989


Thank you for updating your status.

Looking at your simulation waveform, it seems that your MIPI CSI-2 TX design is sending out some data.
If you are sending HS data, LP clock will not toggling. This is an expected result.
Initialization procedure seems to be good. If you do not see buffer underrun, you are doing fine.


1. Could you please share the waveform zoom around LP-->HS transition and HS-->LP transition ?
2. How do you connect your MIPI output to Sink device ? ( We suggest to use external device such as Meticom MC20002)

 

Are you still seeing some issue ?

 

Best regards
Leo

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Re: MIPI CSI-2, D-phy Tx - No Video Output, No mipi_out_clk_lp

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@karnanl

 

We are using a Meticom MC20902 PHY.

 

In simulation I ran for several video frames and never saw the lp clock.  I expected the core to switch from HS to LP at the end of each video frame.

 

Can you please confirm that this is what should happen with the settings I have?

 

It will take me a little while to get the waveforms that you've requested in hardware since I'm debugging another issue that creates video for the MIPI core.  I didn't see an issue with it in simulation.  As soon as it is resolved I'll get the waveforms you requested.

 

Thanks,

Bruce

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Re: MIPI CSI-2, D-phy Tx - No Video Output, No mipi_out_clk_lp

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@karnanl,

 

I fixed the ISERDES2 issue I needed to add the phase delay mentioned in AR 57966 so I'll get the waveforms you requested soon.

 

Regards,

Bruce

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Re: MIPI CSI-2, D-phy Tx - No Video Output, No mipi_out_clk_lp

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Hello @sparky989

Thank you for sharing your update.

 

If you are sending video data in HS mode only, you will never see lp_clk toggling.

I think you are doing good.

 

If you are sending data in Low power mode (escape mode) then you will see lp_clk toggling.

Do you use Escape mode ??

 

BTW, I am interested to see the HW waveform.

 

Best regards

Leo

 

View solution in original post

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Re: MIPI CSI-2, D-phy Tx - No Video Output, No mipi_out_clk_lp

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@karnanl,

 

Here are scope waveforms from our board looking at one of the 4 MIPI lanes produced by our Meticom DPHY.  The MIPI HS data from the FPGA and HS clock look good.  We can't easily access the LP data from the FGPA but I'll provide LP waveforms from an ILA soon.

 

I had thought that MIPI automatically switched between LP and HS mode every frame.  That is what we've scene when using a dedicated MIPI chip in another application.

 

Is there a setting in the MIPI core over the AXI bus that would do this?  Would it be a once and done setting or would it have to be issued every frame?

 

thanks and Regards,

Bruce

ultra mipi transition 2.png
ultra mipi transition issue at dphy.png
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Re: MIPI CSI-2, D-phy Tx - No Video Output, No mipi_out_clk_lp

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@karnanl,

 

Section 6.3 of the mipi DPHY spec. v2.1 states, "During normal operation a Data Lane will be either in Control or High-Speed mode. High-Speed Data 426 transmission happens in bursts and starts from and ends at a Stop state (LP-11), which is by definition in 427 Control mode. The Lane is only in High-Speed mode during Data bursts. The sequence to enter High-Speed 428 mode is: LP-11, LP-01, LP-00 at which point the Data Lane remains in High-Speed mode until a LP-11 is 429 received."

 

Table 2 in the standard distinguishes Low Power control mode and escape mode.

 

The LP control mode is that one that I was expecting.  Does it require anything to be in the MIPI Tx core to achieve and and would it require an LP clock and LP data to be generated from the MIPI Tx core in the FPGA to the D-PHY, or would the D-PHY do this on its own?

 

Thanks and Regards,

Bruce

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Re: MIPI CSI-2, D-phy Tx - No Video Output, No mipi_out_clk_lp

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@karnanl,

 

Leo,

 

I've found in our Meticom MC20902 D-phy spec (attached) Fig. 5 that it does expect to see the LP11 (stop) -> LP01 -> LP00 data on the LP bus in order to add this stop to HS data transmission request (per 6.3 of MIPI D-phy spec v2.1) in its MIPI output, so I would expect that there must be a way to produce this, and I think it occurs during vertical blanking but I haven't absolutely confirmed this in the standard yet.  

 

Please try to get back to me soon since this is a black box I'm not going to be able to figure this out on my own.

 

thanks,

Bruce

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Re: MIPI CSI-2, D-phy Tx - No Video Output, No mipi_out_clk_lp

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Hello Bruce @sparky989

 

 

1. Your sim result seems to be okay.

2. MIPI specification clearly stated we have to support

(a) Continuous mode (Mandatory)

(b) Non-continuous clock mode (optional)

3. MIPI CSI-2 TX IP has default setting set as Continuous clock mode. Clock lane will continue to transmit HS clock even if data lane in LP mode.

4. If you want to use non-continuous clock mode, please change the register configuration at addr offset 0x04.

 

Question :

a. Do you have any problem on HW interoperability test with current MIPI IP behavior ?

 

Hope this helps.

 

Thanks

Leo

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Re: MIPI CSI-2, D-phy Tx - No Video Output, No mipi_out_clk_lp

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@karnanl,

 

Hi Leo,

 

Our SOC is currently not decoding the MIPI input but I've reviewing with our software group.

 

I've attached one more scope photo showing one of the MIPI D-PHY outputs single ended and I kind of see an LP11 to LP01 to LP00 LP to HS burst mode start.

 

I've attached an ILA logic analyzer view of the LP_P[3:0] and LP_N[3:0] outputs and there I see LP11 to LP01 to LP00 transition before the HS data starts.  On the other side I see an LP11 stop  to stop the HS burst.

 

Please confirm that the MIPI core is supposed to insert the LP to HS and HS to LP transaction automatically at vertical blanking even without the use of escape code and without sending LP control data.

 

I'll hopefully get more answers from our software team soon.

 

Thanks,

Bruce

 

mipi dphy diff pair p is yello, n is blue.png
VSYNC trailing edge has LP11 to LP01 to LP00 HS start.png
hs to LS11 stop state.png
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Re: MIPI CSI-2, D-phy Tx - No Video Output, No mipi_out_clk_lp

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Hello Bruce @sparky989
Thank you for the update.

1. I have a look on you Oscilloscope waveform.
    I believe your system LP-01 output signal is not correct (violated MIPI spec).
    Your SoC may not be able to recognize it as LP-01, so MIPI IP on your SoC will not start LP-->HS transition.
    Could you confirm that please ? ( Is there any FSM, error flag you can share ? )
2. BTW, From your ILA capture, I can see that Xilinx MIPI TX IP is sending LP-11, LP-01, LP-11.
    So the problem could be somewhere Meticom IC and SoC.
3. (Just for my reference) Could you tell me please what Vivado version you are using right now ?


Thanks & regards
Leo

MIPI_FORUM_BRUCE.png
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Re: MIPI CSI-2, D-phy Tx - No Video Output, No mipi_out_clk_lp

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@karnanl

Hi Leo,

 

I was also somewhat concerned about the LP01 transition.  Is it possible that if our SOC software driver isn't in the MIPI mode so that it isn't presenting the proper terminations?

 

When you asked about the FSM error flag are you referring to the reads from the MIPI CSI-2 Tx controller interrupt register?

 

I will check that on the ILA.  I am not currently doing anything if there is an error but I am sitting in a loop and continuously reading it.

 

Thanks and Regards,

Bruce

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Re: MIPI CSI-2, D-phy Tx - No Video Output, No mipi_out_clk_lp

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@karnanl,

Leo,

 

I am using Vivado 2018.1.

 

Bruce

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Re: MIPI CSI-2, D-phy Tx - No Video Output, No mipi_out_clk_lp

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Hello Bruce @sparky989

 

1. MIPI LP mode does not require termination on ther RX side. Termination is enabled during HS-ZERO period.

    after RX can detect LP-11, LP-01, LP-00 transtition.

2. I mean the error flag of the SoC on your system, what the Device say ?

    They device should have some error flag, that may help us to detect the current status.   

3. Affirmative on Vivado 2018.1

 

Best regards

Leo

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Re: MIPI CSI-2, D-phy Tx - No Video Output, No mipi_out_clk_lp

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@karnanl (Leo),

 

Thanks,

 

 I sent the same photo of the MIPI D-phy output to Meticom and they think that our SOC not properly turning off the 100 ohm differential termination for HS mode when in LP mode.  Our SOC supplier says that they do this so I think our software driver may not be in the MIPI mode. I'm awaiting software support from our group that does the software driver.

 

Thanks for all your help so far.  I'd like to leave this open for a while  until I get some software support from my group.

 

Regards,

Bruce

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Re: MIPI CSI-2, D-phy Tx - No Video Output, No mipi_out_clk_lp

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@karnanl, Leo,

 

Can you please confirm the polarity of the mipi_video_if_mipi_vid_hsync, and mipi_video_if_mipi_vid_vsync?

 

Based upon the native interface figure B-3 in pg260-mipi-csi2-tx.pdf it appears that VSYNC is asserted high and HSYNC is asserted low (active video when VSYNC is 0 and HSYNC is 1).  See the attached bitamp.

 

Is this correct?

 

Should I only see the HS to LP transition occur during vertical or horizontal blanking since it seems to occur outside this time also?

 

Thanks and Regards,

Bruce

pg260-mipi-csi2-tx native interfaces.jpg
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Re: MIPI CSI-2, D-phy Tx - No Video Output, No mipi_out_clk_lp

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Hello Bruce @sparky989

 

1. No, vid_hsync, vid_vsync is active-high signal. as described in Fig B-3.

    When you assert vid_vsync, you MIPI core will transmit Short Packet for Frame start. 

2. MIPI IP expected vid_hsync to be asserted high during HS transmission.

3. If you see HS-->LP transition occur during video transition. (vid_hsync==high)

    Please check for  pixel under-run or buffer overflow (at Interrupt Status Register)

 

 

Could you please share the simulation result with us ?

 

Best regards

Leo

 

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Re: MIPI CSI-2, D-phy Tx - No Video Output, No mipi_out_clk_lp

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@karnanl (Leo),

 

I'm confused by your response.  You say that hsync should be high during HS so please confirm that you mean that hsync should be high during active horizontal video  when the video is sent in HS mode and low otherwise.  

 

That is what I current have.  I referred to this as hsync active low since the sync period when there's no active video hsync is low.

 

For vsync however i have vsync low during vertically active video and high during vertical blanking.

 

That appears to be what fig. b-3 is showing.

Is that correct?

 

Thanks,

Bruce

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Re: MIPI CSI-2, D-phy Tx - No Video Output, No mipi_out_clk_lp

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@karnanl (Leo),

 

Here is an ILA logic analyzer capture showing the lp_p and lp_n high when mipi_vid_enable is 1, mipi_vid_vsync =0 and mipi_vid_hsync=1.  I don't know if there were any errors during this particular capture since I don't have an ILA on the AXI data.  I don't have a processor connected to the AXI bus of the MIPI core, I'm using a state machine within the FPGA to interface to it.  I am working on an interface to our processor to expose the ISR register to our processor though but it will take some time since it depends upon software from another site.

 

 

Kitkat3 1080p30, single LVDS LP transitionsjpg.jpg
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Re: MIPI CSI-2, D-phy Tx - No Video Output, No mipi_out_clk_lp

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@karnanl (Leo),

 

As I've mentioned previously we are not including the front porch and back porch that are shown in Fig b-3.  If they are required can you please specify their duration?  

 

Here is the logic we have.  yhblank is high during horizontal blanking and yvblank is high during vertical blanking.  That still appears to be what is in figure b-3.

 

mipi_video_if_mipi_vid_enable <= not yhblank and not yvblank;
mipi_video_if_mipi_vid_hsync <= not yhblank; -- so hsync low during horizontal blanking

mipi_video_if_mipi_vid_vsync <= yvblank;   -- so vsync high during vertical blanking.

 

Thanks,

Bruce

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Re: MIPI CSI-2, D-phy Tx - No Video Output, No mipi_out_clk_lp

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Hello Bruce @sparky989

 

> please confirm that you mean that hsync should be high during active horizontal video when the video is sent in HS mode and low otherwise.

 

Yes. hsync should be high during active horizontal video when the video is sent in HS mode and low otherwise.

 

> For vsync however i have vsync low during vertically active video and high during vertical blanking.

 

Yes. That should work.

 

> we are not including the front porch and back porch that are shown in Fig b-3. If they are required can you please specify their duration?

 

Okay. PG260 is not clear with HBP/HFP requirement.
I will need to check with development team to clarify this.

 

Could you please re-upload the ILA ? , since I cannot confirm the screenshot.

 

Thanks & regards
Leo

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Re: MIPI CSI-2, D-phy Tx - No Video Output, No mipi_out_clk_lp

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Hi @karnanl (Leo),

 

Per you request I am re-uploading the ILA capture showing an LP to HS transition occurring when HSYNC is high and one also shows mipi_enable is high.

 

Thanks,

Bruce

Ultra 1080p60 MIPI LP  to HS transition when HSYNC is high (active video).gif
Kitkat3 1080p30, single LVDS LP transitionsjpg.jpg
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Re: MIPI CSI-2, D-phy Tx - No Video Output, No mipi_out_clk_lp

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Hello Bruce @sparky989

 

Confirmed that we should add at least 1 s_axis_aclk clock period for HBP & HFP.

MIPI CSI-2 TX will send synchronous short packet (Line start) on vid_hsync L-->H,

and send Line-end on vid_hsync H-->L. ( see pictures from the CSI-2 spec. )

 

I will ask MIPI team to enhance PG232 PG260 for future release.

Adding HBP/HFP requirement and perhaps provide a better resolution on Figure B-3.

--Please let me know if you SoC still have difficulty receiving signal from Xilinx MIPI CSI-2 TX.

 

BTW :

1. Is your SoC RX ready to receive MIPI signal ? ( I believe you are discussing with your software team )

    I still have a concern on your LP-->HS transition waveform (Since I cannot see LP-11/LP-01/LP-00)

2. Is there any error flag (related to MIPI) reported on your SoC (MIPI RX) ?

 

Best regards

Leo

CSI_TX_Native_for_Bruce.png
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Re: MIPI CSI-2, D-phy Tx - No Video Output, No mipi_out_clk_lp

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@karnanl (Leo),

 

Thanks!  I will make this change tomorrow or the next day.

 

I am still waiting for my software team in Germany to start to work on the software driver.  Something else has priority now.  I'm hoping they start on it ASAP.  I suspect the video input from our SOC may not be in MIPI mode based upon the bad signal integrity we've seen in the HS to LP transition.

 

I haven't noticed errors.  I've modified an LED to indicate if the Interrupt Status Register is not all 0s (no errors).

I've also modified our software interface so our processor can read the MIPI Interrupt status register and tell the FPGA to reset the MIPI core upon an error.

 

Another two questions about changing number of active lanes, and recovering from a MIPI error. 

1. pg260 pg 40 under general checks states that "if you encounter any errors to disable and re-enable the core to clear any stale data stored in the buffers."  It would be simpler in my state machine to issue the AXI reset and to read the core until Core controller is ready in core config register, write # of MIPI lanes to protocol config reg. and re-enable the core.

 

Will that work?

 

2. In my application a user can change my camera from 1080p50/59.94/60 to 1080p25/29.97/30 mode and our plan was to dynamically change the number of MIPI lanes from 4 lanes to 2 lanes when this happens so that the initialized data rate per lane won't change.

 

What is the correct process to do this?  I was again thinking of resetting the core, and setting it up again with the revised number of MIPI lanes.

 

Will that work?  Is there a disadvantage to doing this this way such as the video being down for a longer period of time and if so how long.

 

Thanks, 

Bruce 

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Re: MIPI CSI-2, D-phy Tx - No Video Output, No mipi_out_clk_lp

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@karnanl (Leo),

 

I finally got some feedback from our software team.

 

Can you please comment on their findings about apparent missing EOF messages?

thanks,

Bruce

 

But today, I finally found enough time to continue the work on the MIPI configuration. In the meantime, I see in the Ambarella VIN port status registers:

 

  • the MIPI lanes toggle between low power and high speed mode
  • some probably reasonable size of 3840 byte for the “long” packets ( I assume the size is calculated across the lanes)
  • reasonable horizontal pixel counter
  • SOF packets received
  • Assuming 1080 long packets per frame, roughly 1 short packet per frame (this seems to be similar to CFA-MIPI-sensors

 

However,

 

  • The vertical line counter gets ridiculously high (normally, since it is reset with every frame, it should stay below 1080)
  • EOF packets are not detected
  • Frame sync errors (unpaired SOF/EOF packets; this may be a startup issue, as I see this error bit also set on other MIPI cameras)
  • The iDSP crashing with the incoming video stream (only 2 DSP IRQ1 issued, normally I should get one per frame)

 

Is it possible that the EOF packets are missing or incorrect in the data stream?

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Re: MIPI CSI-2, D-phy Tx - No Video Output, No mipi_out_clk_lp

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@karnanl (Leo),

 

Please also see my previous 2 messages.

 

I made the change to have a 1 axi clock front porch and back porch as shown in the below 3 diagram.

I did NOT change vertical sync so I am still sending vertical blanking to the MIPI cores vertical sync.

Please confirm that is OK.

 

Please confirm that these diagrams look OK particularly the relationship between video_pixel data and the enable since some data may be getting cut off.

 

I should find out tomorrow how this change affects our SOC.

 

Thanks,

Bruce

 

 

hsync change 1.jpg
hsync change 2.jpg
hsync change 3jpg.jpg
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Re: MIPI CSI-2, D-phy Tx - No Video Output, No mipi_out_clk_lp

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Hello Bruce @sparky989

 

What version on Vivado you are using ?
(We have some issue with CSI-2 TX IP on older IP version. https://www.xilinx.com/support/answers/69766.html)

 

>1. pg260 pg 40 under general checks states that "if you encounter any errors to disable
>and re-enable the core to clear any stale data stored in the buffers."
>It would be simpler in my state machine to issue the AXI reset and to read the core
>until Core controller is ready in core config register, write # of MIPI lanes to
>protocol config reg. and re-enable the core.
>Will that work?

 

Yes. I found similar statement in PG260 page 42.
If you mean by providing IP hard-reset (s_axis_aresetn), then thats will do.


>2. In my application a user can change my camera from 1080p50/59.94/60 to 1080p25/29.97/30
>mode and our plan was to dynamically change the number of MIPI lanes from 4 lanes to 2 lanes
when this happens so that the initialized data rate per lane won't change.
>
>What is the correct process to do this? I was again thinking of resetting the core, and setting
>it up again with the revised number of MIPI lanes.

 

As described in PG260 Chapter 3:

The Protocol Configuration Register [1:0] can be used to dynamically configure the active
lanes used by the subsystem using the following guidelines:
1. Program the required lanes in the Protocol Configuration register only when the following conditions are met:
a. “Enable Active Lanes” is set in the Vivado IDE
b. There is no ongoing transfer on the PPI and all the data lanes are in the stop-state
2. Do not send the new updated lanes traffic until the read from Protocol Configuration
registers reflects the new value.


>I did NOT change vertical sync so I am still sending vertical blanking to the MIPI cores vertical sync.
>Please confirm that is OK.

 

Please let confirm on this.
(1) If you set vid_vsync=1, MIPI CSI-2 TX will send SoF packet.
      Please set vid_vsync=1 only when you want to send SoF packet.
      ( Note EoF packet is send automatically, if you are sending the SoF of next frame )
(2) Please set vid_vsync=0, when you are sending your video data. (as stated in PG260 Figure B-3)

-- If your system is following (1)and(2), then your vid_vsync is good.
(BTW, your modification on vid_hsync is good.)


>However,
>1. The vertical line counter gets ridiculously high
>(normally, since it is reset with every frame, it should stay below 1080)
>2. EOF packets are not detected
>3. Frame sync errors (unpaired SOF/EOF packets; this may be a startup issue, as I see this error bit also set on other MIPI cameras)
>4. The iDSP crashing with the incoming video stream (only 2 DSP IRQ1 issued, normally I should get one per frame)

 

If you are using the latest Vivado. These are not an expected result.
Could you please tell me your Vivado version ?

-- Is this possible to share your Vivado the simulation testbench with me ?


Best regards
Leo