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Adventurer
Adventurer
1,597 Views
Registered: ‎01-19-2018

MIPI CSI -2 DPHY HS mode

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Hello,

On K7 family series:-

1. Low power state (LPS) insertion between the packets. What's the fashion of the transition for the High-SPeed mode?
LP00->LP01->LP11

2. In pg:no27 of pg260-MIPI-csi2-tx transition LP11 is explaining what?

3. We want CSI-2 DPhy in High-Speed mode what are the transitions initially the controller generates to CSI-2 Rx in regards the LP to HS?

4. Does CSI Tx packetizes 8 bits into a byte?

5. What is the data word for YUV_422 like RGB888 has 0x24?

Regards,
Prasanna Kumar Daram

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Xilinx Employee
Xilinx Employee
1,556 Views
Registered: ‎03-30-2016

Re: MIPI CSI -2 DPHY HS mode

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Hello Prasanna @daram123

 

Some of your questions are regarding MIPI protocol specification. Could you please take sometime to read these.

For MIPI D-PHY specification please check: https://members.mipi.org/wg/All-Members/document/folder/8358

For MIPI CSI-2 specification please check : https://members.mipi.org/wg/All-Members/document/folder/8367

 

1. Low power state (LPS) insertion between the packets. What's the fashion of the transition for the High-SPeed mode?

 

MIPI starts from LP mode, to change to HS mode, we have the following transition for both clock/data lanes.

LP11-->LP01->LP00->HS

XF_MAG_TRANSITION_LP_HS.png


2. In pg:no27 of pg260-MIPI-csi2-tx transition LP11 is explaining what?

 

I do not understand this question.

I cannot find LP11 keyword in page 27.

https://www.xilinx.com/support/documentation/ip_documentation/mipi_csi2_tx_subsystem/v2_0/pg260-mipi-csi2-tx.pdf


3. We want CSI-2 DPhy in High-Speed mode what are the transitions initially the controller generates to CSI-2 Rx in regards the LP to HS?

 

(a) ensure all clocks are stable

(b) Follow reset sequence mentioned in PG260 Figure 3-4.

(c) set core enable.

(d) put pixel data into AXI4-stream input I/F (recommend to use AXI4-stream I/F instead of Native interface)

For details see PG260 chapter3.


4. Does CSI Tx packetizes 8 bits into a byte?

 

Yes


5. What is the data word for YUV_422 like RGB888 has 0x24?

 

Hmm, I believe you are asking for Data type.

For YUV422 8 bit, Data type=0x1E. (This is mentioned in CSI-2 specification Chapter11)

 

Thanks  & regards

Leo

 

9 Replies
Xilinx Employee
Xilinx Employee
1,557 Views
Registered: ‎03-30-2016

Re: MIPI CSI -2 DPHY HS mode

Jump to solution

Hello Prasanna @daram123

 

Some of your questions are regarding MIPI protocol specification. Could you please take sometime to read these.

For MIPI D-PHY specification please check: https://members.mipi.org/wg/All-Members/document/folder/8358

For MIPI CSI-2 specification please check : https://members.mipi.org/wg/All-Members/document/folder/8367

 

1. Low power state (LPS) insertion between the packets. What's the fashion of the transition for the High-SPeed mode?

 

MIPI starts from LP mode, to change to HS mode, we have the following transition for both clock/data lanes.

LP11-->LP01->LP00->HS

XF_MAG_TRANSITION_LP_HS.png


2. In pg:no27 of pg260-MIPI-csi2-tx transition LP11 is explaining what?

 

I do not understand this question.

I cannot find LP11 keyword in page 27.

https://www.xilinx.com/support/documentation/ip_documentation/mipi_csi2_tx_subsystem/v2_0/pg260-mipi-csi2-tx.pdf


3. We want CSI-2 DPhy in High-Speed mode what are the transitions initially the controller generates to CSI-2 Rx in regards the LP to HS?

 

(a) ensure all clocks are stable

(b) Follow reset sequence mentioned in PG260 Figure 3-4.

(c) set core enable.

(d) put pixel data into AXI4-stream input I/F (recommend to use AXI4-stream I/F instead of Native interface)

For details see PG260 chapter3.


4. Does CSI Tx packetizes 8 bits into a byte?

 

Yes


5. What is the data word for YUV_422 like RGB888 has 0x24?

 

Hmm, I believe you are asking for Data type.

For YUV422 8 bit, Data type=0x1E. (This is mentioned in CSI-2 specification Chapter11)

 

Thanks  & regards

Leo

 

Adventurer
Adventurer
1,535 Views
Registered: ‎01-19-2018

Re: MIPI CSI -2 DPHY HS mode

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@karnanl
>HS has a 400mv range and LP has a 1.2V after HS does the transition occurs on the pins of HS mode?

FPGA has LVDS pins. Do they support 1.2V and 400 mV and also the transitions?

CSI -2 Tx generates the transitions?

Regards,
Prasanna Kumar Daram

Adventurer
Adventurer
1,515 Views
Registered: ‎01-19-2018

Re: MIPI CSI -2 DPHY HS mode

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Is "10"&x"4" same as x"24"?

Regards,
Prasanna Daram

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Xilinx Employee
Xilinx Employee
1,506 Views
Registered: ‎03-30-2016

Re: MIPI CSI -2 DPHY HS mode

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Hello Prasanna Kumar @daram123

 

>FPGA has LVDS pins. Do they support 1.2V and 400 mV and also the transitions?

 

(Answer is no)

 

Opps, it seems you are using 7-series devices. We do highly recommended to use US+ devices (any model) for MIPI I/F.

7-series device does not have I/O that support MIPI D-PHY natively. If you want to use  7-series you will need to use external PHY device (for example device from Meticom).

 

>CSI -2 Tx generates the transitions?

 

Yes.

MIPI CSI-2 TX Subsystem has MIPI D-PHY TX IP inside. MIPI D-PHY TX IP responsible to generate LP->HS, HS->LP transition.

 

>is "10"&x"4" same as x"24"?

 

Pardon me, I do not understand this question.

 

Thanks & regards

Leo

Adventurer
Adventurer
1,495 Views
Registered: ‎01-19-2018

Re: MIPI CSI -2 DPHY HS mode

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@karnanlK7 and FPGA D-PHY generate the transitions. to Pass it forward to external devices we need Meticom MC20902. Does this setup carry the transitions of LP->HS and HS->LP?

Regards,
Prasanna Daram

Xilinx Employee
Xilinx Employee
1,489 Views
Registered: ‎03-07-2018

Re: MIPI CSI -2 DPHY HS mode

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Hi @daram123

 

As per my knowledge, Answer is yes.

For more information check xapp894-d-phy-solutions.pdf (Specifically  Page18~20)

 

Regards,

Bhushan

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Bhushan

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Adventurer
Adventurer
1,461 Views
Registered: ‎01-19-2018

Re: MIPI CSI -2 DPHY HS mode

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@karnanl The word count for RGB888 1920x1080p60 is x"1680". What it is in a Dual Pixel per beat?

Regards,
Prasanna Daram

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Xilinx Employee
Xilinx Employee
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Registered: ‎03-30-2016

Re: MIPI CSI -2 DPHY HS mode

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Hello @daram123

 

1. Word count = 1920 pixel x 3 byte = 5760 (dec) = 0x1680. This is the number of byte in 1 HS packet.

    Details explanation can be found in MIPI CSI-2 specification

2. Same answer for Dual pixel per beat.

     SInce the word count does not change.

 

Hope this helps.

 

Thanks & regards

Leo

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Adventurer
Adventurer
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Registered: ‎01-19-2018

Re: MIPI CSI -2 DPHY HS mode

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Hello @bpatil>>
The XAPP Dphy doesn't specify the METICOM MC20902 GPIO lines, to be set to MIPI Dphy or LVDS to SLVS conversion. pg-no 4 in this document gives enough details for METICOM Conversion.

Regards,
Prasanna Daram