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Adventurer
Adventurer
2,642 Views
Registered: ‎09-02-2018

Re: MIPI CSI-2 RX Subsystem + OV5647 problem on Ultra96 (ZU3EG)

@hokim, sure.

 

Here you have the:

The steps to build the project would be something like:

  • download the Ultra96 BSP and create a PetaLinux project from it
  • update the project-spec folder with the above one
  • import the Vivado Project, run Synthesis and Implementation, generate Bitstream, Export Hardware including bitstream
  • update the PetaLinux project with the new hardware definition
  • build PetaLinux, populate an SD card with the build images (boot + root partition)
  • boot from the SD card

I will add a more detailed description here, when the whole project is complete:

https://www.hackster.io/bluetiger9/stereo-vision-and-lidar-powered-donkey-car-575769

 

Cheers,

Attila

Observer soc4video
Observer
2,592 Views
Registered: ‎11-01-2018

Re: MIPI CSI-2 RX Subsystem + OV5647 problem on Ultra96 (ZU3EG)

@bluetiger9

Great work!  Could you include pr-built binaries (BOOT.BIN, Image and system-top.dtb)?

Thanks.

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Adventurer
Adventurer
2,563 Views
Registered: ‎09-02-2018

Re: MIPI CSI-2 RX Subsystem + OV5647 problem on Ultra96 (ZU3EG)

Observer soc4video
Observer
2,551 Views
Registered: ‎11-01-2018

Re: MIPI CSI-2 RX Subsystem + OV5647 problem on Ultra96 (ZU3EG)

@bluetiger9,

Thanks for the binaries, they worked same as the binaries I built using you Vivado and petalinux projects files.

The LED on Pi camera turned on, there is "/dev/video0" listed as Video capture Multiplaner, 1920/0 'YUYV'.

I did not see sub devices.  How did you capture video?  E.g., what command/parameters of v4l2-ctl did you use?

Thanks

 

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Adventurer
Adventurer
2,535 Views
Registered: ‎09-02-2018

Re: MIPI CSI-2 RX Subsystem + OV5647 problem on Ultra96 (ZU3EG)

@soc4video, try these:

# MIPI RX:
$ media-ctl -v -d /dev/media0 -V '"80120000.mipi_csi2_rx_subsystem":0 [fmt:SBGGR8/640x480]'
$ media-ctl -v -d /dev/media0 -V '"80120000.mipi_csi2_rx_subsystem":1 [fmt:SBGGR8/640x480]'# Demosaic
$ media-ctl -v -d /dev/media0 -V '"b0050000.v_demosaic":1 [fmt:RBG24/640x480]'
# Gamma LUT
$ media-ctl -v -d /dev/media0 -V '"b0070000.v_gamma_lut":1 [fmt:RBG24/640x480]'
# SS CSC
$ media-ctl -v -d /dev/media0 -V '"b0040000.v_proc_ss":1 [fmt:RBG24/640x480]'
# SS SCALER
$ media-ctl -v -d /dev/media0 -V '"b0000000.v_proc_ss":1 [fmt:UYVY/640x480]'

Then you should be able to capture some frames using Yavta. The format need to be UYVY.

 

Thanks,

Attila

Observer soc4video
Observer
2,520 Views
Registered: ‎11-01-2018

Re: MIPI CSI-2 RX Subsystem + OV5647 problem on Ultra96 (ZU3EG)

@bluetiger9

I did not see "/dev/media0".  Do you mean "/dev/video0"?

Thanks

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Adventurer
Adventurer
2,505 Views
Registered: ‎09-02-2018

Re: MIPI CSI-2 RX Subsystem + OV5647 problem on Ultra96 (ZU3EG)

@soc4video, /dev/media0 is probably missing, because one of the video pipeline components (the OV5647 + the ones from PL) was not successfully probed by the kernel drivers. You could check the kernel log for errors.

Observer soc4video
Observer
2,502 Views
Registered: ‎11-01-2018

Re: MIPI CSI-2 RX Subsystem + OV5647 problem on Ultra96 (ZU3EG)

I did not realize I also need the rootfs from your Petalinux project.  I was using rootfs from @hokim.

I see "/dev/media0" now.  Thanks

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Observer soc4video
Observer
2,493 Views
Registered: ‎11-01-2018

Re: MIPI CSI-2 RX Subsystem + OV5647 problem on Ultra96 (ZU3EG)

It's weird, "/dev/media0" disappeared again and I could not get it back after reset or power cycle.  "dmesg" shows "media: Linux Media Interface V0.10" 

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Adventurer
Adventurer
2,486 Views
Registered: ‎09-02-2018

Re: MIPI CSI-2 RX Subsystem + OV5647 problem on Ultra96 (ZU3EG)

@soc4video, try booting with:

$ setenv bootargs 'loglevel=8 earlycon clk_ignore_unused root=/dev/mmcblk0p2 rw rootwait dynamic_debug.verbose=1 dyndbg="module *xilinx* +pm ; module ov5647 +pm ; file drivers/media/* +pm ; module *i2c* +pm"'
$ boot 

You should see messages for each of the video pipeline components:

  • OV5647
  • MIPI CSI-2 Rx Subsystem
  • Demosaic
  • Gamma LUT
  • CSC
  • Scaler
  • Frame Buffer Writer

When each of these were successfully initialized, the V4L2 pipeline is created. After this you should see the /dev/media0 and /dev/v4l-subdev-* nodes.

 

In your case probably one of the components failed. Normally you should have an error message in the kernel log.

 

Thanks,

Attila

Tags (1)
Adventurer
Adventurer
2,332 Views
Registered: ‎09-02-2018

Re: MIPI CSI-2 RX Subsystem + OV5647 problem on Ultra96 (ZU3EG)

Hi @karnanl,

I got the a hardware design with two MIPI video pipelines that boots successfully with PetaLinux.

The 1st video pipeline is working, but in the 2nd one the MIPI CSI-2 RX Subsytem produces the "Stream Line Buffer Full" condition.

I guess something will be wrong with the AXI streaming interfaces between the video pipeline components. But, the two video pipeline are identical, so I don't know why just the second one produces this problem.

Can you tell us what this "Stream Line Buffer Full" condition exactly means?

I posted more info, including register values, here:
https://forums.xilinx.com/t5/Embedded-Linux/PetaLinux-hangs-on-custom-Ultra96-platform/m-p/908511/highlight/false#M30150

Thanks,
Attila

 

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Xilinx Employee
Xilinx Employee
2,322 Views
Registered: ‎03-30-2016

Re: MIPI CSI-2 RX Subsystem + OV5647 problem on Ultra96 (ZU3EG)

Hello Attila @bluetiger9

MIPI CSI-2 RX subsystem has a line buffer inside the core. "Stream Line Buffer Full"  means this buffer is full :-)
User have to set video_out_tready=1 that indicate backend modules are ready to read-out data from MIPI CSI-2 RX IP line-buffer.
If you never set video_out_tready=1, or video_aclk frequency is too slow, or video_out_tready=1 ratio is too low you might have "Stream Line Buffer Full"  condition.
I took a glance at your MIPI register dump, nothing is weird except for note1.

1. Is the video_aclk you are using for both MIPI CSI-2 RX instances has the same frequency ?
( is it still the same 150MHz as you mentioned in previous post ?)
2. How do you control video_out_tready  of both IPs ?
3. Since both MIPI IP instances have identical IP configuration, if you can confirm that (1) and (2) is okay , I believe the root-cause Is not in the MIPI IP itself.
the video_out_tready could be hold low for a long period by the backend modules. (VPSS perhaps?!)


Thanks & regards
Leo

Note1:
One more thing I see that your video_pipeline_1 has SoTSyncError asserted. This is not good.
Could you please check if SoTSyncError occurs every time ?

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Adventurer
Adventurer
2,316 Views
Registered: ‎09-02-2018

Re: MIPI CSI-2 RX Subsystem + OV5647 problem on Ultra96 (ZU3EG)

Hi @karnanl,

1. both video pipelines are using the same 175 Mhz clock

2. the video pipeline components are connected using AXI Streaming interface as:

MIPI CSI 2 RX => Demosaic => Gamma LUT => VPSS Color Space Conversion => VPSS Scaler => Frame Buffer Write

The video_out_tready for each component is generated by next component in the pipeline. So, in the of MIPI CSI 2 RX the video_out_tready is generated by the Demosaic module.

3. I suspect each component sets is video_out_tready=1 only after it got video_out_tready=1 from the next component in the pipeline. This means the problem could be caused by any of the video pipeline components.

At the first glance, something seems to be wrong with the VPSS Scaler component, more exactly with its H control register (offset 0x00):

VPSS Scaler
 0x00000 (h control) = 0xBF ?! wrong ?!
 0x20000 (v control) = 0x00000081 (ap_start + auto restart)

I made a quick test with devmem and looks like that register behaves faulty:

  • reads shows wrong value (0x3F instead of 0x04):

 

root@Ultra96:~# devmem 0xb0000000 32    # vp1, scaler H control
0x00000004   <-- OK
root@Ultra96:~# devmem 0xb0020000 32    # vp1, scaler V control
0x00000004   <-- OK

root@Ultra96:~# devmem 0xb0080000 32    # vp2, scaler H control
0x0000003F   <-- WRONG
root@Ultra96:~# devmem 0xb00a0000 32    # vp2, scaler V control
0x00000004   <-- OK
  • write is not working properly

 

# vp1, H control
root@Ultra96:~# devmem 0xb0000000 32 0x00000084
root@Ultra96:~# devmem 0xb0000000 32           
0x00000084   <-- OK

# vp1, V control
root@Ultra96:~# devmem 0xb0020000 32 0x00000084
root@Ultra96:~# devmem 0xb0020000 32
0x00000084   <-- OK

# vp2, H control
root@Ultra96:~# devmem 0xb0080000 32 0x00000084
root@Ultra96:~# devmem 0xb0080000 32
0x000000BF   <-- WRONG, write=0x84, read back=0xBF

# vp2, V control
root@Ultra96:~# devmem 0xb00a0000 32 0x00000084
root@Ultra96:~# devmem 0xb00a0000 32
0x00000084   <-- OK

Do you have an idea what could cause such a behaviour?

Thanks,
Attila

 

 

 

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Xilinx Employee
Xilinx Employee
2,187 Views
Registered: ‎03-30-2016

Re: MIPI CSI-2 RX Subsystem + OV5647 problem on Ultra96 (ZU3EG)

Hello Attila @bluetiger9

1. If you are using video_aclk=175MHz for both MIPI IP, then it should be fine.

3. Your understanding is correct, that this problem could be caused by any of the video pipeline component.

@kshimizu, @florentw  Could you please provide some valuable direction to Attila on VPSS debugging ??

Thanks & regards
Leo

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Moderator
Moderator
2,180 Views
Registered: ‎11-09-2015

Re: MIPI CSI-2 RX Subsystem + OV5647 problem on Ultra96 (ZU3EG)

HI @bluetiger9,

From my understanding, both VPSS does not have the same configuration. I am not sure if their register map is the same.

Where this H and V controls are coming from? From my understanding there should be only one address for the control register of the VPSS


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Adventurer
Adventurer
2,173 Views
Registered: ‎09-02-2018

Re: MIPI CSI-2 RX Subsystem + OV5647 problem on Ultra96 (ZU3EG)

Hi @florentw,

I have two identical video pipelines in my design. The only difference between them is the pins used for the MIPI CSI-2 D-PHY.

The problem is that, depending on the design parameters (clocks, etc.), only one of them is working properly.

I was able to produce .BIN files in which the 1st video pipeline is working and .BIN files in which the 2nd video pipeline is working. But never got a .BIN file with both of the video pipelines working properly.

The video pipeline which is not working, usually produces the "Stream Line Buffer Full" error. Sometimes the AXI read / write does not seems to work property. I had .BIN files in which AXI operation causes hangs.

At the first glance, it seems that HLS does not produces 100% reliable results for the video pipeline components. Even if there are no errors or critical warnings.

Thanks,
Attila

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Moderator
Moderator
2,168 Views
Registered: ‎11-09-2015

Re: MIPI CSI-2 RX Subsystem + OV5647 problem on Ultra96 (ZU3EG)

Hi @bluetiger9,

If it is working when you are using only one pipe, then I do not think this is an issue with the HLS IP.

Could you do test outside linux? Export the hdf to SDK and try to do the same register configuration from the xsct console (using mwr and mrd commands)


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Adventurer
Adventurer
2,121 Views
Registered: ‎09-02-2018

Re: MIPI CSI-2 RX Subsystem + OV5647 problem on Ultra96 (ZU3EG)

Hi @florentw,

I din not tried to use the two video pipelines at same time. I'm using them one at a time.

The problem is that with any given design (.BIN file), if PetaLinux can boot with that design (some designs fail this early), only one of the video pipelines is working correctly (ex. /dev/video1), while the another one is producing error (ex. /dev/video0).

With a given design (.BIN file), the video pipeline that is works is the same (ex. /dev/video1), but can change between the designs (for ex. /dev/video0). Note: /dev/video0 corresponds to the 1st video pipeline in Vivado, while /dev/video1 to the 2nd video pipeline.

By "does not produces 100% reliable results" I meant the .BIN files produces by Vivado simply does not always work, even if the synthesis and implementation is done without errors or critical warnings.

Unfortunately, I cannot use the xsct console as I don't have the JTAG adapter for the Ultra96.

I tried to play around in the with SDK different test application and their behavior is a little bit strange.

For example the Peripheral Test produces this result:

 

---Entering main---

 Running IntcSelfTestExample() for axi_intc_0...
IntcSelfTestExample PASSED

 Running ScuGicSelfTestExample() for psu_acpu_gic...
ScuGicSelfTestExample PASSED
ScuGic Interrupt Setup PASSED

Running CsiSsSelfTestExample() for mipi_csi2_rx0_mipi_csi2_rx_subsyst_0...
CsiSs_SelfTestExample PASSED

 Running XZDma_SelfTestExample() for psu_adma_0...
XZDma_SelfTestExample PASSED

 Running Interrupt Test  for psu_adma_0...  <<< GETS STUCK

I had also tried to read / write:

 

   {
	   int status;

	   print("\r\n Try writing to VPSS Scaler 1...\r\n");
	   Xil_Out32(XPAR_MIPI_CSI2_RX1_V_PROC_SCALER_0_HSC_S_AXI_CTRL_BASEADDR, 0x04);
	   print("\r\n - write OK. trying read back...\r\n");
	   if (0x04 == Xil_In32(XPAR_MIPI_CSI2_RX1_V_PROC_SCALER_0_HSC_S_AXI_CTRL_BASEADDR)) {
		   print("\r\n - read back OK\r\n");
	   } else {
	       print("\r\n - read back WRONG\r\n");
	   }

	   print("\r\n Try writing to VPSS Scaler 0...\r\n");
	   Xil_Out32(XPAR_MIPI_CSI2_RX0_V_PROC_SCALER_0_HSC_S_AXI_CTRL_BASEADDR, 0x04);
	   print("\r\n - write OK. trying read back...\r\n");
	   if (0x04 == Xil_In32(XPAR_MIPI_CSI2_RX0_V_PROC_SCALER_0_HSC_S_AXI_CTRL_BASEADDR)) {
		   print("\r\n - read back OK\r\n");
	   } else {
		   print("\r\n - read back WRONG\r\n");
	   }
   }

Now it seems to work:

 

 

 Try writing to VPSS Scaler 1...

 - write OK. trying read back...

 - read back OK

 Try writing to VPSS Scaler 0...

 - write OK. trying read back...

 - read back OK

but I had designs in which AXI read / write got stuck in the SDK, while PetaLinux booted with the same design and one of the Video Pipeline components are working.

Any ideas?

 

Thank,
Attila

 

 

 

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Moderator
Moderator
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Registered: ‎11-09-2015

Re: MIPI CSI-2 RX Subsystem + OV5647 problem on Ultra96 (ZU3EG)

Hi @bluetiger9,

No I am not sure what can be the issue.

Maybe you can increase a bit the clock of the VPSS. Maybe it just at the limit for providing enough data for the pipe.


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Adventurer
Adventurer
2,105 Views
Registered: ‎09-02-2018

Re: MIPI CSI-2 RX Subsystem + OV5647 problem on Ultra96 (ZU3EG)

Hi @florentw,

We are far from the maximum throughput of the video pipeline. I'm trying with 640x480 resolution. 640 x 480 pixels x 30 fps = 9,216,000 pixels / s

The video pipelines are running @150 Mhz. In 1 pixel per clock configuration (as my latest design is configured), they should be able to process: 150,000,000 pixels / s.

I see two possible causes for problem:

  • Vivado is generating unstable bit stream - maybe some of my settings / constrains are wrong and this causes the synthesis and implementation to succeed

  • damaged / faulty hardware - I'm not sure how likely is this

@sandeepg mentioned that you have a team working on the MIPI CSI-2 design for Ultra96 with the same MIPI adapter I'm using:
https://forums.xilinx.com/t5/Embedded-Linux/PetaLinux-hangs-on-custom-Ultra96-platform/m-p/909255/highlight/true#M30205

Maybe they could provide some help to investigate this issue. What do you think?

Thanks,
Attila

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Moderator
Moderator
2,106 Views
Registered: ‎11-09-2015

Re: MIPI CSI-2 RX Subsystem + OV5647 problem on Ultra96 (ZU3EG)

HI @bluetiger9,

I was not aware there will be an example design for Ultra96 and MIPI. However, I do not think they will help to investigate this issue.

But if there is a design in 2018.3, then it could be a good reference. I already asked to get the MIPI Adapter. Hopefully I will get it this quarter.

Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Adventurer
Adventurer
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Registered: ‎09-02-2018

Re: MIPI CSI-2 RX Subsystem + OV5647 problem on Ultra96 (ZU3EG)

Hi @florentw,

Maybe, they could send me the example design, so I could check it out for differences compared to my design. I understood that the 2018.3 will be released somewhere in December, but I would not wait until then if not necessary. It's ok for me if the design is not fully finalized yet.

In addition, along the OV5645 you're using, we could validate the design with the OV5647 camera module too.

Can you ask them if this is possible?

Thanks,
Attila

 

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Moderator
Moderator
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Registered: ‎11-09-2015

Re: MIPI CSI-2 RX Subsystem + OV5647 problem on Ultra96 (ZU3EG)

Hi @bluetiger9,

I do not think this is possible to get the design before it is released.


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Adventurer
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Registered: ‎09-02-2018

Re: MIPI CSI-2 RX Subsystem + OV5647 problem on Ultra96 (ZU3EG)

@florentw, understood. Then, I think we need to figure out what could cause the problem inmy design.

Could this be a hardware problem? If yes, how we can confirm this?

If not, then the problem is probably in the implemented design or maybe is some setting that makes the SoC unstable.

I think we could start with the Peripheral Test that gets stuck at the "Interrupt Test for psu_adma_0" for some reason. The tests from the Peripheral Test are expected to PASS as they are generated by the SDK, right?

Thanks,
Attila

Moderator
Moderator
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Registered: ‎11-09-2015

Re: MIPI CSI-2 RX Subsystem + OV5647 problem on Ultra96 (ZU3EG)

HI @bluetiger9,

I would think there is something unstable in the design more than on the HW. But we cannot exclude that this could be a HW issue.

Yes I would believe the Peripheral Test should pass but there might be something SDK is incorrectly configuring based on your configuration, or your configuration of the PS might not be expected for the test.  The only way to check is to go in the code and check where it fails.

Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Re: MIPI CSI-2 RX Subsystem + OV5647 problem on Ultra96 (ZU3EG)

Hi @florentw,

The Peripheral Test fails because of a bug in the XDMA / CDMA and UART drivers from the test. For some reason, if there is an AXI Interrupt Controller present in the design, that is used instead of the internal PSU_ACPU_GIC. (makes a lot of sense !?)

After fixing it hacking it to work, the self test passes:

Xilinx Zynq MP First Stage Boot Loader 
Release 2018.2   Nov 22 2018  -  23:06:26
PMU-FW is not running, certain applications may not be supported.
---Entering main---

 Running IntcSelfTestExample() for axi_intc_0...
IntcSelfTestExample PASSED

 Try writing to VPSS Scaler 1...

 - write OK. trying read back...

 - read back OK

 Try writing to VPSS Scaler 0...

 - write OK. trying read back...

 - read back OK

 Running ScuGicSelfTestExample() for psu_acpu_gic...
ScuGicSelfTestExample PASSED
ScuGic Interrupt Setup PASSED

Running CsiSsSelfTestExample() for mipi_csi2_rx0_mipi_csi2_rx_subsyst_0...
CsiSs_SelfTestExample PASSED

 Running XZDma_SelfTestExample() for psu_adma_0...
XZDma_SelfTestExample PASSED

 Running Interrupt Test  for psu_adma_0...

ZDMA Simple Example PASSED

 Running XZDma_SelfTestExample() for psu_adma_1...
XZDma_SelfTestExample PASSED

 Running Interrupt Test  for psu_adma_1...

ZDMA Simple Example PASSED

 Running XZDma_SelfTestExample() for psu_adma_2...
XZDma_SelfTestExample PASSED

 Running Interrupt Test  for psu_adma_2...

ZDMA Simple Example PASSED

 Running XZDma_SelfTestExample() for psu_adma_3...
XZDma_SelfTestExample PASSED

 Running Interrupt Test  for psu_adma_3...

ZDMA Simple Example PASSED

 Running XZDma_SelfTestExample() for psu_adma_4...
XZDma_SelfTestExample PASSED

 Running Interrupt Test  for psu_adma_4...

ZDMA Simple Example PASSED

 Running XZDma_SelfTestExample() for psu_adma_5...
XZDma_SelfTestExample PASSED

 Running Interrupt Test  for psu_adma_5...

ZDMA Simple Example PASSED

 Running XZDma_SelfTestExample() for psu_adma_6...
XZDma_SelfTestExample PASSED

 Running Interrupt Test  for psu_adma_6...

ZDMA Simple Example PASSED

 Running XZDma_SelfTestExample() for psu_adma_7...
XZDma_SelfTestExample PASSED

 Running Interrupt Test  for psu_adma_7...

ZDMA Simple Example PASSED

 Running SysMonPsuPolledPrintfExample() for psu_ams...

Entering the SysMon Polled Example. 

The Current Temperature is 29.798 Centigrades.
The Maximum Temperature is 29.961 Centigrades. 
The Minimum Temperature is 29.098 Centigrades. 

The Current VCCINT is 0.854 Volts. 
The Maximum VCCINT is 0.855 Volts. 
The Minimum VCCINT is 0.852 Volts. 

The Current VCCAUX is 1.810 Volts. 
The Maximum VCCAUX is 1.811 Volts. 
The Minimum VCCAUX is 1.807 Volts. 

Exiting the SysMon Polled Example. 
SysMonPsuPolledPrintfExample PASSED

 Running SysMonPsuIntrExample()  for psu_ams...

Entering the SysMonPsu Interrupt Example. 

The Current Temperature is 29.697 Centigrade.

The Current VCCINT is 0.853 Volts. 

The Current VCCAUX is 1.809 Volts. 

Temperature Alarm(0) HIGH Threshold is 19.695 Centigrade. 
Temperature Alarm(0) LOW Threshold is 9.693 Centigrade. 
VCCINT Alarm(1) HIGH Threshold is 0.653 Volts. 
VCCINT Alarm(1) LOW Threshold is 1.053 Volts. 
VCCAUX Alarm(3) HIGH Threshold is 1.609 Volts. 
VCCAUX Alarm(3) LOW Threshold is 2.009 Volts. 

Alarm 0 - Temperature alarm has occured 

The Current Temperature is 29.984 Centigrade.
The Maximum Temperature is 30.342 Centigrade. 
The Minimum Temperature is 29.199 Centigrade. 

The Current VCCINT is 0.853 Volts. 
The Maximum VCCINT is 0.856 Volts. 
The Minimum VCCINT is 0.851 Volts. 

The Current VCCAUX is 1.810 Volts. 
The Maximum VCCAUX is 1.811 Volts. 
The Minimum VCCAUX is 1.806 Volts. 

Exiting the SysMon Interrupt Example. 
SysMonPsu IntrExample PASSED

 Running XCsuDma_SelfTestExample() for psu_csudma...
XCsuDma_SelfTestExample PASSED

 Running Interrupt Test  for psu_csudma...
CSUDMA Interrupt Example PASSED

 Running XZDma_SelfTestExample() for psu_gdma_0...
XZDma_SelfTestExample PASSED

 Running Interrupt Test  for psu_gdma_0...

ZDMA Simple Example PASSED

 Running XZDma_SelfTestExample() for psu_gdma_1...
XZDma_SelfTestExample PASSED

 Running Interrupt Test  for psu_gdma_1...

ZDMA Simple Example PASSED

 Running XZDma_SelfTestExample() for psu_gdma_2...
XZDma_SelfTestExample PASSED

 Running Interrupt Test  for psu_gdma_2...

ZDMA Simple Example PASSED

 Running XZDma_SelfTestExample() for psu_gdma_3...
XZDma_SelfTestExample PASSED

 Running Interrupt Test  for psu_gdma_3...

ZDMA Simple Example PASSED

 Running XZDma_SelfTestExample() for psu_gdma_4...
XZDma_SelfTestExample PASSED

 Running Interrupt Test  for psu_gdma_4...

ZDMA Simple Example PASSED

 Running XZDma_SelfTestExample() for psu_gdma_5...
XZDma_SelfTestExample PASSED

 Running Interrupt Test  for psu_gdma_5...

ZDMA Simple Example PASSED

 Running XZDma_SelfTestExample() for psu_gdma_6...
XZDma_SelfTestExample PASSED

 Running Interrupt Test  for psu_gdma_6...

ZDMA Simple Example PASSED

 Running XZDma_SelfTestExample() for psu_gdma_7...
XZDma_SelfTestExample PASSED

 Running Interrupt Test  for psu_gdma_7...

ZDMA Simple Example PASSED

 Running IicPsSelfTestExample() for psu_i2c_1...
IicPsSelfTestExample PASSED

Running CsiSsSelfTestExample() for mipi_csi2_rx1_mipi_csi2_rx_subsyst_0...
CsiSs_SelfTestExample PASSED

 Running SpiPsSelfTestExample() for psu_spi_0...
SpiPsSelfTestExample PASSED

 Running SpiPsSelfTestExample() for psu_spi_1...
SpiPsSelfTestExample PASSED

 Running Interrupt Test  for psu_ttc_0...
TtcIntrExample PASSED

 Running Interrupt Test  for psu_ttc_3...
TtcIntrEx�UartPsPo�UartPsIntrExample PASSED

But, I'm still have no glue what problem with the video pipeline is.

Attila

 

 

 

Moderator
Moderator
1,953 Views
Registered: ‎11-09-2015

Re: MIPI CSI-2 RX Subsystem + OV5647 problem on Ultra96 (ZU3EG)

HI @bluetiger9,

It would help if you had the JTAG board. This way you could add an ILA in the streams to maybe see what is wrong.

Maybe you can try to shorten the video pipes. Did you already try with 2 TPGs (no MIPI interface)?


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
Moderator
Moderator
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Registered: ‎04-24-2017

Re: MIPI CSI-2 RX Subsystem + OV5647 problem on Ultra96 (ZU3EG)

Hi @bluetiger9,

We can't share the design until the release is out.

Please watch for 2018.3 PetaLinux release notes for more details once we release.

Thanks,
Sandeep
PetaLinux Yocto | Embedded SW Support

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Adventurer
Adventurer
1,936 Views
Registered: ‎09-02-2018

Re: MIPI CSI-2 RX Subsystem + OV5647 problem on Ultra96 (ZU3EG)

Hi @florentw,

Yeah, having JTAG may help. Probably, I will pick a JTAG/UART Adapter for the Ultra96 on my next Farnell order.

Meantime, I started playing around with SDSocC and xfOpenCV. I created a custom SDSoC platform with MIPI x2 design and stared trying out different examples. The first 2 examples (array partitioning on standalone + array partitioning on PetaLinux) worked OK, but the 3rd (HW accelarated Harris corner detection) does not works yet.

But, as the PetaLinux booted successfully, I decided to check the video pipelines with the SDx generated bitstream. Surprisingly, the yavta capture worked, so I made a Python + OpenCV script to capture some PNG images using. What I got is:

stereo.jpg

As you can see the left image (/dev/video0) has some kind of noise. The noise is coming from video pipeline. To confirm this, I swapped the cameras and on /dev/video0 I got the noise with both the cameras.

Any idea what could cause this kind of noise?

Thanks,
Attila

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Moderator
Moderator
1,918 Views
Registered: ‎11-09-2015

Re: MIPI CSI-2 RX Subsystem + OV5647 problem on Ultra96 (ZU3EG)

Hi @bluetiger9,

No idea of what could really be the issue but it loks like the red color is saturated. Maybe it is coming form one of the openCV block used?


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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