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Visitor 8bitmode
Visitor
439 Views
Registered: ‎04-26-2019

MIPI CSI-2 RX truncated frame lines

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Hello,

I'm debugging an issue on the Xilinx ZCU102 board where I've configured an external camera sensor and the MIPI CSI-2 RX subsystem to receive RAW8 images with 640x480 resolution at 60 fps.  I'm starting from a working design (including the camera sensor board being used) that can successfully pass a live video stream.  However I only need a subset of this larger design.

The symptoms I'm seeing in the hardware debugger waveform window are:

  • TUSER[0] produced by the CSI-2 RX video AXIS logic is 4 clocks wide, and not a single clock wide pulse as I believe it should be
  • Horizontal lines appear to be 580 pixels long, and not 640 pixels long; this was measured by the length of TVALID (while TREADY was also asserted) during a transfer of a horizontal line on the AXIS bus
  • The CSI-2 IRQ Status register in the core is flagging a Word Count (WC) error condition; I'm not sure if this error condition is correlated with the above two issues, or not

The truncated number of pixels per line (580 vs. 640) is causing downstream issues in some image processing IP that I'm integrating into the design, and I can only get 7 complete "truncated" lines to ingress into this image processing IP before its AXIS-slave logic hangs (keeping its TREADY toward the CSI-2 RX AXIS-master deasserted forever).

I've read on a separate forum post that a multi-cycle TUSER[0] pulse indicates a failed configuration issue in the CSI-2 RX core.  I've attempted to replicate the solution from that forum post in my SW project, but so far no success.

Here is that URL, for reference:  https://forums.xilinx.com/t5/Video/tuser-is-kept-more-than-one-cycle-in-mipi-csi-2-rx-subsystem/td-p/957043

Since I'm starting from a working design (both HW and SW pieces are demonstratably functional), I know it's simply a matter of CSI-2 RX core configuration and/or SW configuration causing the above issues.

Any suggestions and tips are greatly appreciated!

Thank you

-8bitmode

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Visitor 8bitmode
Visitor
228 Views
Registered: ‎04-26-2019

Re: MIPI CSI-2 RX truncated frame lines

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Hi @karnanl 

Thanks for those notes, very helpful.

Good news--I was able to resolve the issue, which indeed was related to effective clock frequency as you suggested, by cutting the sensor clock in half (divide by 2) via sensor provisioning.  No changes in CSI-2 RX Subsystem register configuration were required.  I will keep the TUSER "filter" RTL in place for now, since this also was part of the overall solution for my specific use case.

I will plan to update this post/issue as "resolved".

Thanks so much for your help!

-8bitmode

11 Replies
Xilinx Employee
Xilinx Employee
380 Views
Registered: ‎03-30-2016

Re: MIPI CSI-2 RX truncated frame lines

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Hello @8bitmode 

>TUSER[0] produced by the CSI-2 RX video AXIS logic is 4 clocks wide, and not a single clock wide pulse as I believe it should be

Yes. This is a know issue and will be fixed on Vivado 2019.2 IP.
If your FPGA design is based on MIPI CSI-2 RX Subsystem Example Design, this unexpected behavior should not cause any issue.


>Horizontal lines appear to be 580 pixels long, and not 640 pixels long; this was measured by the length of TVALID (while TREADY was also asserted) during a transfer of a horizontal line on the AXIS bus
>The CSI-2 IRQ Status register in the core is flagging a Word Count (WC) error condition; I'm not sure if this error condition is correlated with the above two issues, or not


I am suspecting that your video_aclk frequency is too low. (See also PG232 Chapter 3 for IP clocks calculation )
Could you please share your usecase, so we can double check for you ? (Please share your XCI. Screenshot will do)

Thanks & regards
Leo

Visitor 8bitmode
Visitor
375 Views
Registered: ‎04-26-2019

Re: MIPI CSI-2 RX truncated frame lines

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Hi Leo,

Thanks for your assistance.

I've written a small piece of RTL that both (1) filters TUSER to produce a one-clock-wide pulse version thereof, and (2) extends the 560 truncated line to a full 640 pixels.  This interim remedy is allowing my device under test to stream AXIS frames without hanging up, so this is a nice next-step.

Now, to reclaim those 640 - 580 = 60 missing pixels :)

Thanks for the pointer to PG232 Ch 3.  I will check that out.  For my application, the clock frequencies I'm currently using are:

  • video_aclk = 40 MHz (also used for all downstream AXIS devices, including device under test)
  • dphy_clk_200M = 200 MHz (no surprise there)
  • camera clock = 24 MHz

Input image is 640x480 60 fps RAW8 .

In regards to the XCI, which XCI should I provide in particular?

Thanks!

-8bitmode

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Xilinx Employee
Xilinx Employee
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Registered: ‎03-30-2016

Re: MIPI CSI-2 RX truncated frame lines

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Hello @8bitmode 

Could you please share xci file of your MIPI CSI-2 RX Subsystem ?

Thanks & regards
Leo

Note: You cannot upload file with *xci* extention in the Forum

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Visitor 8bitmode
Visitor
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Registered: ‎04-26-2019

Re: MIPI CSI-2 RX truncated frame lines

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Hi @karnanl 

Ah Ok.  Please find the XCI file for the subsystem below.

Thanks!

-8bitmode


<?xml version="1.0" encoding="UTF-8"?>
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<spirit:componentInstance>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CSIRXSS_S_AXI.RUSER_BITS_PER_BYTE">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CSIRXSS_S_AXI.RUSER_WIDTH">0</spirit:configurableElementValue>
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Visitor 8bitmode
Visitor
330 Views
Registered: ‎04-26-2019

Re: MIPI CSI-2 RX truncated frame lines

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Hi @karnanl 

To provide further info, after studying Table 3-2 in PG232, here are the corresponding clock rates for my design:

  • rxbyteclkhs = (840 M) / 8 = 105 M
  • core clock = (105 M) (2 / 4) = 52.5 M
  • pixel clock = (52.5 M) / (32 / 8) = 13.125 M
  • video clock = (13.125 M) / 1 = 13.125 M  (minimum required value...)

I'm using video_aclk = lite_aclk = 40 MHz > video clock, which seems to be sufficiently fast for the application.

On a related clocking note, PG232 (Table 3-1) states that the user should attach clkoutphy_out to clkoutphy_in when "Include Shared logic in core" option is selected.  I see clkoutphy_out listed on the block design port symbol, but do not see clkoutphy_in listed on the port symbol.  So, I assume this required connection is being taken care of automatically by the tools?

Thanks again for your help,

-8bitmode

 

Xilinx Employee
Xilinx Employee
290 Views
Registered: ‎03-30-2016

Re: MIPI CSI-2 RX truncated frame lines

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Hello @8bitmode 

Could you please increase your video_aclk to 210MHz or higher ?
I believe your usecase is something like this :
IN_OUT_MIPI.png


If you are using video_aclk > 210MHz, and the issue remains observed,
Please share your all MIPI CSI-2 RX register dump. I can double check the result.

Thanks & regards
Leo

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Visitor 8bitmode
Visitor
276 Views
Registered: ‎04-26-2019

Re: MIPI CSI-2 RX truncated frame lines

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Hi @karnanl 

Thanks for your suggestion.  I will try to dial up the video_aclk rate as suggested.  Though I'm not sure the IP-under-test can run this fast.

Just curious, but was my computation of video_aclk incorrect?  I calculated minimum video_aclk = 13.125 MHz using the formulae in Table 3-2 of PG232.  Perhaps I misunderstood the terms in the equations?

Thanks

-8bitmode

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Xilinx Employee
Xilinx Employee
246 Views
Registered: ‎03-30-2016

Re: MIPI CSI-2 RX truncated frame lines

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Hello @8bitmode 

Please notice that we mentioned the "max" term in the clock frequency calculation formula.PG232_cal_for_video_clock.png

Regards
Leo

Visitor 8bitmode
Visitor
229 Views
Registered: ‎04-26-2019

Re: MIPI CSI-2 RX truncated frame lines

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Hi @karnanl 

Thanks for those notes, very helpful.

Good news--I was able to resolve the issue, which indeed was related to effective clock frequency as you suggested, by cutting the sensor clock in half (divide by 2) via sensor provisioning.  No changes in CSI-2 RX Subsystem register configuration were required.  I will keep the TUSER "filter" RTL in place for now, since this also was part of the overall solution for my specific use case.

I will plan to update this post/issue as "resolved".

Thanks so much for your help!

-8bitmode

Xilinx Employee
Xilinx Employee
198 Views
Registered: ‎03-30-2016

Re: MIPI CSI-2 RX truncated frame lines

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Hello @8bitmode 

Thank you for updating your status.

Regards
Leo

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Adventurer
Adventurer
118 Views
Registered: ‎06-05-2019

Re: MIPI CSI-2 RX truncated frame lines

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Hi @8bitmode 

I'm using the MIPI CSI-2 RX subsystem on the Xilinx ZCU102 board with my own camera sensor as you do. The sensor sends 12bit raw image with 1280x720 resolution at 60 fps in two mipi data line.

The problem I meet was posted in the follow link D-PHY module can output signal but no video_out in mipi csi example design  I am very hopeful that you can share your successful experience such as what changes need to be made to the configuration of RX Subsystem and the xmipi_example program in SDK. Do other IPs need to be changed in addition to RX Subsystem in RX Subsystem example design?

Thank you in advance.

 

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