[MIPI CSI-2 Rx subsystem : Pixel packing for RAW10]

[uuoo93]

Hell. I am working on ZCU102 evaluation board and Vivado HLx system suite version 2018.2.(Window O.S) I am using MIPI CSI-2 Rx subsystem v3.0 and refer to pg232 document, but there is a little unclear information in pixel packing.

I want to know pixel packing for RAW10 when using Video Format Bridge with two pixels per clock. According to pg232 document, I can get information about pixel packing for RAW12, RAW8, RAW6 when using Video Format Bridge with two pixels per clock as shown below figure 1. Based on this, I can guess RAW10 pixel packing when using Video Format Bridge with two pixels per clock as shown below figure 2, but I want to make this clear.

<Figure 1>

<Figure 2>

I want to get a definite answer on this because there is a possibility that it is figure 3 as shown below.

<Figure 3>

Thank you for taking your time to read this post. Any help is greatly appreciated!

[karnanl]

Hello @uuoo93

Yes, for MIPI CSI-2 RX from 2018.2. Your understanding is correct.

But please be careful, from MIPI IP from 2018.3 and later version.
The data output format will be MSB justified. ( MIPI CSI-2 RX will follow guideline from UG934).
Hope you don't get confused.

Thanks & regards
Leo

[ziladdev]

Happy I found this thread.

I am using the v4.0 of the IP core, and I can confirm that the documentation PG232 states that it will be MSB justified. However, the example has not been changed and this is somehow something that would need to be reported (a bug?).

Using v 4.0 example. the Subset converter seems to map the RAW10 to RAW8 using :

tdata[19:12],tdata[9:2]

which indicates that the RAW10 data was "right" or "LSB" justified as it makes no sense to ignore the MSB while converting from RAW10 to RAW8-

Could anyone from Xilinx confirm this ?

PS: Lacking a CSI-2 camera at the moment but will be able to test this next week.

PS2: please advise if this should be posted in a different thread. 

[karnanl]

Hello @ziladdev

Please give me some time. I will check and give you some feedback on this.

Thanks & regards
Leo

[bpatil]

Hello @ziladdev

It will be better to create new thread for your query. 

[ziladdev]

Done! created a new thread at:

https://forums.xilinx.com/t5/Video/Potential-mismatch-between-documentation-and-example-of-CSI-RX/m-p/937033

[karnanl]

Hello @uuoo93

Do you have any update on this?
If your question is answered, please kindly mark the response which helped as solution (click on "Accept as solution" button below the reply) , so others can learn from your experience.

Thanks and regards
Leo