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Observer kami
Observer
748 Views
Registered: ‎03-18-2017

MIPI CSI-2 TX Clocking

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Hi,

I want to use CSI-2 TX Subsystem IP in my design. I have read PG260 document. My video input is in 720p/50 YUV422 8bit format and I need to transmit it via 4 lanes (Pixel Mode is 1). When I simulate CSI-2 TX Subsystem it gives underrun in Protocol Configuration Register. I guess my s_axis_aclk is wrong.

By my calculation,

1280 x 720 x 50Hz x 16bit = 737.28 Mbit/s

TxByteClk = 737.28 Mbit/s / 8bit = 92.16 MHz

From PG260 : s_axis_aclk x Pixel_width x Pixel_Mode > TxByteClk x No_Lanes x 8     

s_axis_aclk x 16bit x 1 > 92.16 x 4 x 8

s_axis_aclk = 92.16 x 2 x 1.3 ~= 240 MHz

 

Is this correct? If not, please correct me for selecting the right value of s_axis_aclk.

Thanks.

 

 

 

 

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Xilinx Employee
Xilinx Employee
675 Views
Registered: ‎03-30-2016

Re: MIPI CSI-2 TX Clocking

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Hello Kami @kami
Thanks for the update.

>When I simulate CSI-2 TX Subsystem it gives underrun in Protocol Configuration Register. I guess my s_axis_aclk is wrong
>By the way AXI Stream input (m_axis_video_tdata) frequency to CSI-2 TX IP is 74.25MHz.

This is the root-cause of your pixel underrun issue.

Once MIPI CSI-2 TX start sending pixel line data, they have to send all 720pixel data in one line continuously without a gap.
If user cannot supply pixel data by the time CSI-2 TX IP needs to process the data, pixel under-run will be asserted. There is no such as idle-code/idle-data in MIPI CSI-2 specification. This is the reason we provide a guidance for a minimum s_axis_aclk frequency.

If your pixel data source is generated using 74.25MHz, You might need to create a line-buffer to provide input data into MIPI CSI-2 TX IP. Start read the data out from the buffer after you have one line of pixel data.

XF_20181127_PROPOSAL_FOR_KAMI.png

Thanks & regards
Leo

4 Replies
Xilinx Employee
Xilinx Employee
724 Views
Registered: ‎03-30-2016

Re: MIPI CSI-2 TX Clocking

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Hello Kami

TxByteClk = Line Rate / 8.
Since you did not mention your IP line-rate, Could you please re-do the s_axis_aclk calculation ?

Thanks & regards
Leo

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Observer kami
Observer
694 Views
Registered: ‎03-18-2017

Re: MIPI CSI-2 TX Clocking

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Hello @karnanl,

Thanks for your response.

Actually I didn't notice IP's line rate. My target device can receive up to 1.5Gbps per data lane and I guess 720 Mbps line rate is good.

By the way AXI Stream input (m_axis_video_tdata) frequency to CSI-2 TX IP is 74.25MHz. Is there a relation between output line rate and input frequency?

 

With same calculation,

TxByteClk = 720 / 8 = 90 MHz

s_axis_aclk x Pixel_width x Pixel_Mode > TxByteClk x No_Lanes x 8     

s_axis_aclk x 16bit x 1 > 90 x 4 x 8

s_axis_aclk = 90 x 2 x 1.3 = 234 MHz

 

I tried with this frequency and line rate but CSI-2 TX IP didn't transmit any data.

 

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Xilinx Employee
Xilinx Employee
676 Views
Registered: ‎03-30-2016

Re: MIPI CSI-2 TX Clocking

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Hello Kami @kami
Thanks for the update.

>When I simulate CSI-2 TX Subsystem it gives underrun in Protocol Configuration Register. I guess my s_axis_aclk is wrong
>By the way AXI Stream input (m_axis_video_tdata) frequency to CSI-2 TX IP is 74.25MHz.

This is the root-cause of your pixel underrun issue.

Once MIPI CSI-2 TX start sending pixel line data, they have to send all 720pixel data in one line continuously without a gap.
If user cannot supply pixel data by the time CSI-2 TX IP needs to process the data, pixel under-run will be asserted. There is no such as idle-code/idle-data in MIPI CSI-2 specification. This is the reason we provide a guidance for a minimum s_axis_aclk frequency.

If your pixel data source is generated using 74.25MHz, You might need to create a line-buffer to provide input data into MIPI CSI-2 TX IP. Start read the data out from the buffer after you have one line of pixel data.

XF_20181127_PROPOSAL_FOR_KAMI.png

Thanks & regards
Leo

Observer kami
Observer
666 Views
Registered: ‎03-18-2017

Re: MIPI CSI-2 TX Clocking

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Hi @karnanl,

Thank you for your quick and detailed answer.

I will try the line buffer solution. Before trying it, I wonder if I adjust the IP line rate with keeping AXI-Stream clock same as 74.25MHz. I guess it will also work.

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