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Participant jplynch
Participant
1,419 Views
Registered: ‎03-23-2018

MIPI CSI-2 TX SS - DPHY Simulation model - INIT_DONE shows 'X' and stays low after power-on reset

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This screenshot shows the first 2,000 nS of a simulation of MIPI CSI-2 TX SS configured with shared logic in the core, referred to as a "Master" interface.  Although the Master DPHY's s_axis_resetn signal is inactive (high), the core_rst signal is active right at time=0nS.  The signals under the divider "proc_sys_reset_0" are from the same hierarchy level as the DPHY.  Apparently the IP generator puts this automatic reset block into the subsystem to provide the necessary reset of the DPHY; no user interaction required.  The core_rst seems to be tied to the peripheral_reset of this block.

 

The issue:  INIT_DONE shows an 'X' and will not go high after the initial power-on reset.

 

Note: A "Slave" configuration of the MIPI CSI-2 TX SS (shared logic in the example design) presents the same behavior.

CSI_reset_n_screen1b.JPG

1 Solution

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Xilinx Employee
Xilinx Employee
1,506 Views
Registered: ‎03-30-2016

Re: MIPI CSI-2 TX SS - DPHY Simulation model - INIT_DONE shows 'X' and stays low after power-on reset

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Hello John  @jplynch

Thank you very much for sharing your simulation result !!
I am glad you can confirm that INIT_DONE is also asserted on your FPGA design.

Yes, unfortunately MIPI IP simulation takes a lot of time.
Mainly because MIPI D-PHY TX has a big INIT_VAL value as default setting.

Please see PG202 Table 2-22 for INIT_VAL register explanation.
(for MIPI D-PHY TX : 1 ms, for MIPI D-PHY RX : 100 us )

During initialization process MIPI TX needs to set output lanes into LP-11 state, to make initialization process successful. You can adjust your INIT_VAL setting to meet your system requirement. (Please refer to MIPI D-PHY specification for more detailed information )

So, if you want to run a shorter/faster simulation,

1. You can use lower INIT_VAL register setting.  ( for example 150us )
    -- Modify the register setting. ( or you can also modify C_INIT setting on your XCI file )
2. You may also try to run the simulation using another simulator (if you have access to simulator other than Vivado Simulator).  I found NCSIM runs a lot faster.

Best regards
Leo

XF_JOHN_DPHY_INIT_VAL_REG.png
14 Replies
Xilinx Employee
Xilinx Employee
1,390 Views
Registered: ‎03-30-2016

Re: MIPI CSI-2 TX SS - DPHY Simulation model - INIT_DONE shows 'X' and stays low after power-on reset

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Hello John @jplynch

 

I found that the XCI generated from IP Integrator (sent by you), and same XCI generated from IP catalog has different setting. ( Note : I am using the same Vivado & targeting the same device ).

For example the following parameter has different setting.

 

 

IP generated from
Vivado IP catalog

IP generated from
Vivado IP generator

C_EN_BUFG_ON_WR_CLK_OUT

true

False

C_FIFO_RD_EN_CONTROL

true

False

 

I am giving this feedback to our MIPI team, to find out if this difference cause the INIT_DONE not asserted problem.

Could you please confirm if those two parameters has "true" setting on your working project ?

 

Best regards

Leo

 

# Shared this post with : @florentw

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Participant jplynch
Participant
1,380 Views
Registered: ‎03-23-2018

Re: MIPI CSI-2 TX SS - DPHY Simulation model - INIT_DONE shows 'X' and stays low after power-on reset

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Hello Leo,

I have looked through various levels of my simulation model hierarchy and found various "C_" parameters but not the two which you mentioned. Can you tell me where to find this information?

Thanks,
John
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Xilinx Employee
Xilinx Employee
1,369 Views
Registered: ‎03-30-2016

Re: MIPI CSI-2 TX SS - DPHY Simulation model - INIT_DONE shows 'X' and stays low after power-on reset

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Hello John @jplynch

 

I have looked through various levels of my simulation model hierarchy and found various "C_" parameters but not the two which you mentioned. Can you tell me where to find this information?

 

Those two parameter can be found in MIPI D-PHY IP XCI file.

These are not a parameter in the IP RTL.

 

Please wait for a feedback from our MIPI developer team.

 

Best regards

Leo

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Participant jplynch
Participant
1,352 Views
Registered: ‎03-23-2018

Re: MIPI CSI-2 TX SS - DPHY Simulation model - INIT_DONE shows 'X' and stays low after power-on reset

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Hi Leo,

Thanks. The values of these parameters are TRUE for both the Master and Slave DPHYs.
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EN_BUFG_ON_WR_CLK_OUT">true</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FIFO_RD_EN_CONTROL">true</spirit:configurableElementValue>

I will wait to hear from the MIPI group.

Regards,
John

Xilinx Employee
Xilinx Employee
1,291 Views
Registered: ‎03-30-2016

Re: MIPI CSI-2 TX SS - DPHY Simulation model - INIT_DONE shows 'X' and stays low after power-on reset

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Hello @jplynch

 

1. Both following parameter should set as true. (expected setting)
    C_EN_BUFG_ON_WR_CLK_OUT = true
    C_FIFO_RD_EN_CONTROL = true

2. I took MIPI D-PHY XCI file from your project, setting those two parameter setting into true,

    and generated the Example design.

    I can confirmed that  INIT_DONE is asserted, and Example Design simulation run without any issue.

3.  Could you please change the setting of those two parameter on the project, and re-run the simulation ?

     You can do it by either

     (a) Modified the XCI by external editor and re-generated the IP.

     (b)Use Vivado tcl console

           set_property -dict [list CONFIG.C_EN_BUFG_ON_WR_CLK_OUT {true}] [get_ips your_ipname

           set_property -dict [list CONFIG.C_FIFO_RD_EN_CONTROL {true}] [get_ips your_ipname

 

4. We still investigating why using IPI give us unexpected parameter setting. Please give us more time to investigate and give you a feedback on this issue.

         C_EN_BUFG_ON_WR_CLK_OUT = false
         C_FIFO_RD_EN_CONTROL = false

 

Best regards

Leo

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Participant jplynch
Participant
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Registered: ‎03-23-2018

Re: MIPI CSI-2 TX SS - DPHY Simulation model - INIT_DONE shows 'X' and stays low after power-on reset

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Hi Leo,

 

I'm glad that you got the simulation to run, but I am confused why I cannot achieve this on my end.  

When I try to run the command you gave me in step 3 b), I get an error as follows:

 

set_property -dict [list CONFIG.C_EN_BUFG_ON_WR_CLK_OUT {true}] [get_ips base_mb_mipi_csi2_tx_subsystem_0_0]
ERROR: [Vivado 12-4371] Cannot find parameter 'C_EN_BUFG_ON_WR_CLK_OUT' on IP 'base_mb_mipi_csi2_tx_subsystem_0_0'.
ERROR: [Vivado 12-1342] Failed to set property 'CONFIG.C_EN_BUFG_ON_WR_CLK_OUT' on IP 'base_mb_mipi_csi2_tx_subsystem_0_0'.
INFO: [Common 17-17] undo 'set_property -dict [list CONFIG.C_EN_BUFG_ON_WR_CLK_OUT {true}] [get_ips base_mb_mipi_csi2_tx_subsystem_0_0]'
ERROR: [Common 17-39] 'set_property' failed due to earlier errors.

 

This is true; my base_mb_mipi_csi2_tx_subsystem_0_0.xci file contains no parameter by this name.  These parameters do exist in the DPHY block files at a lower level, specifically

 

...\Microblaze_Take2.srcs\sources_1\bd\base_mb\ip\base_mb_mipi_csi2_tx_subsystem_0_0\bd_0\ip\ip_2\bd_18c5_mipi_dphy_0_0.xci

 

When I search for these two parameters in the bd_18c5_mipi_dphy_0_0.xci file, I find the values to already be set to TRUE, as mentioned in my previous post.

 

Could there be something else wrong on my end?  

 

Thanks,

John

 

 

 

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Xilinx Employee
Xilinx Employee
1,255 Views
Registered: ‎03-30-2016

Re: MIPI CSI-2 TX SS - DPHY Simulation model - INIT_DONE shows 'X' and stays low after power-on reset

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Hello John @jplynch

1. For the step 3 b), your undertanding is correct.
   You have to target bd_18c5_mipi_dphy_0_0.xci not MIPI CSI-2 TX XCI.

2. Anyway, I tried to generate MIPI CSI-2 TX SS design using 2018.1/2018.2 IP integrator.
   and I can confirmed that MIPI D-PHY IP that both parameters are set to true.
   ( There is nothing wrong with IP generated from IPI since the setting is equal with IP generated from IP catalog)   (   ( So, it must be my mistake on generating D-PHY example design using your XCI, pardon me for the confussion caused)
   
3. Regarding INIT_DONE
   I checked the netlist on MIPI CSI-2 TX IP from your design. (see pictures.)
   Since init_done is not asserted, could you please shared the related signal that generated init_done ??
   Could you probe the following signal from your simulation ?
       - tx_div4_clk
       - init_done_byteclk_r
       - en_clk_init_to_blk.init_done_reg
   It may give us some more valuable hints.

Best regards
Leo

XF_JOHN_INIT_DONE_generation.png
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Participant jplynch
Participant
1,242 Views
Registered: ‎03-23-2018

Re: MIPI CSI-2 TX SS - DPHY Simulation model - INIT_DONE shows 'X' and stays low after power-on reset

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Hello Leo,

 

The plot thickens!  I guess I should have mentioned that I have been running Behavioral Simulation of this model all this time.  The behavioral model is the one that drives INIT_DONE to "X", then low.  The signals that you requested are not available in the behavioral model of MIPI CSI-2 TX; I could not get down deep enough in the model hierarchy to find them.

 

I then decided to run a Post Synthesis Functional Simulation.  Here are the results, with the signals you requested:

INIT_Done_Post_Synth_Sim.JPG

INIT_DONE does not toggle at all in this version.  I ran the simulation out to 110 uS and you do see periodic toggling on the \en_cl_init_to_blk.init_done_reg_i_3_n_3\ and \en_cl_init_to_blk.init_done_reg_i_3_n_2\ lines, but nothing else.

 

So we have two models which do two different things, neither of which is the expected behavior.  I initially wanted to run the Behavioral Simulation because it runs faster.

 

Thanks,

John

 

Participant jplynch
Participant
1,235 Views
Registered: ‎03-23-2018

Re: MIPI CSI-2 TX SS - DPHY Simulation model - INIT_DONE shows 'X' and stays low after power-on reset

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Hello Leo,

 

I believe I have stumbled onto the solution to this problem.  You have to let the simulation run for at least 1 mS for INIT_DONE to go active high.  Your suggestion to trace the lower level signals helped as I found a 14-bit counter down in the netlist which apparently has to reach 1mS before INIT_DONE can go high.

 

Here is the Post-Synthesis Simulation result:

INIT_Done_Post_Synth_Sim_1mS.JPG

 

And here is the Behavioral Simulation result:

INIT_Done_Behavioral_Sim_1mS.JPG

 

It would be nice if the behavioral simulation model had a parameter setting which would allow for the reduction of that counter value, just for simulation.

 

Thanks for the help.  Please let me know if you have additional comments on this issue or the MIPI CSI-2 TX in general.

 

-John

 

Xilinx Employee
Xilinx Employee
1,507 Views
Registered: ‎03-30-2016

Re: MIPI CSI-2 TX SS - DPHY Simulation model - INIT_DONE shows 'X' and stays low after power-on reset

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Hello John  @jplynch

Thank you very much for sharing your simulation result !!
I am glad you can confirm that INIT_DONE is also asserted on your FPGA design.

Yes, unfortunately MIPI IP simulation takes a lot of time.
Mainly because MIPI D-PHY TX has a big INIT_VAL value as default setting.

Please see PG202 Table 2-22 for INIT_VAL register explanation.
(for MIPI D-PHY TX : 1 ms, for MIPI D-PHY RX : 100 us )

During initialization process MIPI TX needs to set output lanes into LP-11 state, to make initialization process successful. You can adjust your INIT_VAL setting to meet your system requirement. (Please refer to MIPI D-PHY specification for more detailed information )

So, if you want to run a shorter/faster simulation,

1. You can use lower INIT_VAL register setting.  ( for example 150us )
    -- Modify the register setting. ( or you can also modify C_INIT setting on your XCI file )
2. You may also try to run the simulation using another simulator (if you have access to simulator other than Vivado Simulator).  I found NCSIM runs a lot faster.

Best regards
Leo

XF_JOHN_DPHY_INIT_VAL_REG.png
Moderator
Moderator
977 Views
Registered: ‎11-09-2015

Re: MIPI CSI-2 TX SS - DPHY Simulation model - INIT_DONE shows 'X' and stays low after power-on reset

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Hi @jplynch,

 

Thank you for sharing. As your issue is solved, could you kindly mark the reply from @karnanl which helped you as accepted solution to close the topic (click on Accept as solution below the reply while logged in).

Also remember give kudos by clicking on the button with a star  kudos.PNG to thanks a user for its reply (it is free ;) )

 

PS: About you comment to reduce the simulation time: For the moment we do not have any simulation test bench for the MIPI CSI-2 IPs. I think if we had, we could do a param to reduce simulation time. I will keep this comment for suggestion if the development team wants to do a simulation test bench.

 

Best Regards


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
Participant jplynch
Participant
963 Views
Registered: ‎03-23-2018

Re: MIPI CSI-2 TX SS - DPHY Simulation model - INIT_DONE shows 'X' and stays low after power-on reset

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Thank you, Leo.

I will reduce these init_val settings just for simulation and leave them as default for the actual implementation in the device. The Vivado simulator is the only one we have at the moment.
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Participant jplynch
Participant
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Registered: ‎03-23-2018

Re: MIPI CSI-2 TX SS - DPHY Simulation model - INIT_DONE shows 'X' and stays low after power-on reset

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Thanks for the help, Florent.

If a MIPI CSI-2 SS testbench were developed, I would definitely make use of it.
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Observer vollerain
Observer
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Registered: ‎06-28-2018

Re: MIPI CSI-2 TX SS - DPHY Simulation model - INIT_DONE shows 'X' and stays low after power-on reset

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Could you please share your simulation tesebench for the xilinx mipi csi2 sub-system? I'm also simlate this IP, and struggling. 

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