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1,156 Views
Registered: ‎07-01-2018

MIPI CSI-2 Tx simulation Vivado 2017.4

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 Hi,

I am attempting CSI 2 TX simulation in vivado 2017.4

Problem  : Data is repeating 2 times in the mipi CSI Tx PHY input.

Steps followed:

1.Generated the TX core with following options

-Line Rate: 800Mbps

-Input video interface: AXI4S

-No of lanes: 4

-Input pixels per beat:1

-Line buffer depth: 4096

-Enabled active lines

-Enabled AXI-4 lite register I/F

-Included shared logic in core 

2.  Followed the configuration sequence attached

//---------------CSI TX CONFIGURATION SEQUENCE-------------------
   
   initial
   begin
    initilize();
    @(posedge s_axis_aresetn);
	
	//================Configuring TX DPHY====================
	
	axi_write(17'h1000,32'h02);
	axi_read(17'h1000);
	if (fbread_data_latch[1] == 1'b1)
		$display($time," DPHY enable Done");
	else
		$display($time," DPHY enable Fail");
	
	//Default value for Tx-DPHY is (32'hF4240) - 1ms
	axi_read(17'h1008);
	$display($time,"DPHY INIT VAL: %h",fbread_data_latch[31:0]);
		
	//Tx-PHY Init value 32'h186A0 - 100us
	axi_write(17'h1008,32'h186A0); 
	axi_read(17'h1008);
	if (fbread_data_latch[31:0] == 32'h186A0)
		$display($time," DPHY INIT value Done");
	else
		$display($time," DPHY initialization Fail");
	
	//====================Configuring TX CORE====================
	
	$display($time,"Waiting for controller ready");
	axi_read(17'h0000);
	while(fbread_data_latch[2] == 1'b0)
	begin
	axi_read(17'h0000);
	end
	$display($time," controller is ready");
	
	axi_read(17'h0004);
	$display($time,"PROTOCOL REG: %h",fbread_data_latch[31:0]);
	
	axi_write(17'h0004,32'h01b);
	axi_read(17'h0004);
    $display($time,"PROTOCOL REG: %h",fbread_data_latch[31:0]);
        
	axi_read(17'h0000);
	axi_write(17'h0000,32'h01);
	
	//=====================Checking for TX PHY INIT Done============
	
	$display($time," Waiting for Tx PHY Init Done");
	axi_read(17'h1018);
	while(fbread_data_latch[3] == 1'b0)
		begin
		axi_read(17'h1018);
		$display($time," waiting for Init done");
		end
	$display($time," Init done");
	
	axi_read(17'h1018);
	if (fbread_data_latch[3] == 1'b1)
		$display($time," Clock Lane Init Done");
	else
		$display($time," Clock Lane Init Fail");
	
	axi_read(17'h101C);
	if (fbread_data_latch[3] == 1'b1)
		$display($time," Data Lane Init Done");
	else
		$display($time," Data Lane Init Fail");
	
	video_resetn <= 1'b1;
	   
	forever
	begin
		axi_read (13'h0024);
		$display("Tx Global Interrupt REG status : %h", fbread_data_latch[31:0]);
		repeat (100) @(posedge s_axis_aclk);
	end
  end 

s_axis_aclk : 160MHz (s_axis_aclk*Pixel_width*Pixel_Mode > TxByteClk*No_Lanes*8*1.2)

s_axis_tdata :  {7'h0,tdata[23:16],6'h0,tdata[15:8],6'h0,tdata[7:0] ,5'h0} (tdata is from video source tpg)

s_axis_tuser : {32'h0,16'h168,16'h0,16'h0,9'h0,6'h24,tuser} (tuser is from video source tpg, word count =120 horizontal pixels * 3 = 360 (0x168), Data type = 0x24(RGB888))

s_axis_tkeep : 0

s_axis_tdest : 0

 

The waveforms are attached.phy_inp_repeated_seq.PNGtx_subsystem_input.PNGvideo_input signals.PNG

 

Can you please help me to find out whether I missed something.?

 

Thank You,

Asya 

 

 

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Xilinx Employee
Xilinx Employee
1,013 Views
Registered: ‎03-30-2016

Re: MIPI CSI-2 Tx simulation Vivado 2017.4

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Hello Asya asya.thomas@tosil

Thanks a lot for sharing your VCD.
Checked the waveform and found that MIPI D-PHY PPI I/F data behavior is expected since you put repetitive data in the MIPI CSI-2 TX input. (Please see the following pictures)

Note:
Yellow = AXI4-stream I/F clock
Red = RGB888 pixel data.
I can see that you tied RED and BLUE pixel to fixed zero. and put a repetitive increment data into GREEN pixel data.
Hope this helps.

 

Thanks & regards
Leo

View solution in original post

XF_20181127_ASYA_MIPI_SIM.png
7 Replies
Xilinx Employee
Xilinx Employee
1,092 Views
Registered: ‎03-30-2016

Re: MIPI CSI-2 Tx simulation Vivado 2017.4

Jump to solution

Hello Asya asya.thomas@tosil

>Problem  : Data is repeating 2 times in the mipi CSI Tx PHY input.

 

I am looking at you waveform trying to understand what your issue is, but I cannot see anything wrong.

So please clarify which which part  is the repeating data ? Please put some red-circle or anything to emphasize it.

 

Thanks & regards
Leo

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1,081 Views
Registered: ‎07-01-2018

Re: MIPI CSI-2 Tx simulation Vivado 2017.4

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I am sending an incremental pattern from my video source (ie, 0,1,2,3,4... ).But when it reaches the TX PHY , observing a pattern like 0,0,1,1,2,2,3,3,4,4...(same data in 2 txbyteclkhs period). 

I also integrated TX with RX. But RX also giving this repeating out (same data is continued for 2 video clock periods in video_out_tdata) different from I expected. 

Observed behavior is marked with red circles in the tx phy signal's waveform.

phy_inp_repeated_seq.PNG

Thank You,

-Asya

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Xilinx Employee
Xilinx Employee
1,050 Views
Registered: ‎03-30-2016

Re: MIPI CSI-2 Tx simulation Vivado 2017.4

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Hello asya.thomas@tosil 
Thanks for the update.

The MIPI D-PHY PPI I/F data is coming from the MIPI CSI-2 RX AXI4-stream I/F (s_axis_tdata).

If you can share your waveform data, I can double check.
Or perhaps you could just share the Vivado waveform screenshot, zoomed at appropriate level so we can   read the signal value.

1. AXI4-stream I/F signals
s_axis_tdata[47:0]
s_axis_tready
s_axis_tvalid
s_axis_user
s_axis_aclk
2. Along with MIPI D-PHY PPI I/F signals
dl*_txdatahs[7:0], dl*_txreadyhs, dl*_txrequesths, txbyteclkhs

Best regards,
Leo

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1,032 Views
Registered: ‎07-01-2018

Re: MIPI CSI-2 Tx simulation Vivado 2017.4

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Hi Leo,

 

Thanks for a quick response. I shared the VCD file via email. Can you please look into that?

 

Regards,

Asya

 

Xilinx Employee
Xilinx Employee
1,014 Views
Registered: ‎03-30-2016

Re: MIPI CSI-2 Tx simulation Vivado 2017.4

Jump to solution

Hello Asya asya.thomas@tosil

Thanks a lot for sharing your VCD.
Checked the waveform and found that MIPI D-PHY PPI I/F data behavior is expected since you put repetitive data in the MIPI CSI-2 TX input. (Please see the following pictures)

Note:
Yellow = AXI4-stream I/F clock
Red = RGB888 pixel data.
I can see that you tied RED and BLUE pixel to fixed zero. and put a repetitive increment data into GREEN pixel data.
Hope this helps.

 

Thanks & regards
Leo

View solution in original post

XF_20181127_ASYA_MIPI_SIM.png
1,001 Views
Registered: ‎07-01-2018

Re: MIPI CSI-2 Tx simulation Vivado 2017.4

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Hi Leo,

 

Thank you so much for your information. 

I corrected the s_axis_tdata input and got the output as expected.

 

Regards,

Asya

Xilinx Employee
Xilinx Employee
992 Views
Registered: ‎03-30-2016

Re: MIPI CSI-2 Tx simulation Vivado 2017.4

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Hello Asya

Thank you for sharing your progress !
I am glad I was able to help.

Kind regards
Leo