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Registered: ‎09-05-2019

MIPI CSI2 Reset

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I'm having an issue with the CSI2 receiver and my suspicion is that the block is not resetting properly.

This is the reset function from xilinx-csi2rxss.c (petalinux 2019.1).  As a test I modified it so that prior to reset it writes a 1 to the interrupt enable register at 0x28 and reads it back prior to the return from the function.   I also added a printk  to the while loop to see if it was ever entered (that is, if bit 0 in the CSR is ever a 1).

What I found is that CSR bit 0 is never set and that the interrupt enable register is not reverting to its reset value of 0.  What would cause the block not to reset?

 

static int xcsi2rxss_reset(struct xcsi2rxss_core *core)
{
   u32 Timeout = XCSI_TIMEOUT_VAL;

   xcsi2rxss_set(core, XCSI_CCR_OFFSET, XCSI_CCR_SOFTRESET_MASK);

   while (xcsi2rxss_read(core, XCSI_CSR_OFFSET) & XCSI_CSR_RIPCD_MASK) {
      if (Timeout == 0) {
         dev_err(core->dev, "Xilinx CSI2 Rx Subsystem Soft Reset Timeout!\n");
        return -ETIME;
      }

      Timeout--; 
      udelay(1);
   }  

  xcsi2rxss_clr(core, XCSI_CCR_OFFSET, XCSI_CCR_SOFTRESET_MASK);
  return 0;
}

 

 

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Xilinx Employee
Xilinx Employee
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Registered: ‎03-30-2016

Re: MIPI CSI2 Reset

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Hello

Great ! Thanks for the update.

IMO, enabling/disabling D-PHY is not necessary when stop/re-start streaming data. I will give this feedback to our Linux Driver team.

 

Thanks & regards
Leo

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Moderator
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Registered: ‎11-09-2015

Re: MIPI CSI2 Reset

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Hi matthew.singer@elbitsystems-us.com 

What command do you use do the soft reset of the core?

Did you add a printk to make sure you were entering in the xcsi2rxss_reset function?


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Registered: ‎09-05-2019

Re: MIPI CSI2 Reset

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Reset is done by writing to bit 1 of the core configuration register

My test code is: 

static int xcsi2rxss_reset(struct xcsi2rxss_core *core)
{
   u32 Timeout = XCSI_TIMEOUT_VAL;   
   u32 val;
   struct gpio_desc *rst = core->rst_gpio;

   xcsi2rxss_write(core, 0x28, 1);
   printk("CSI2 before reset %x\n", xcsi2rxss_read(core, 0x28));   

   xcsi2rxss_set(core, XCSI_CCR_OFFSET, XCSI_CCR_SOFTRESET_MASK);
   printk("CSI2 CSR %x\n", xcsi2rxss_read(core, XCSI_CSR_OFFSET));
   while (val = xcsi2rxss_read(core, XCSI_CSR_OFFSET) & XCSI_CSR_RIPCD_MASK) {
      printk("CSI2 val %x\n", val);
      if (Timeout == 0) {
        dev_err(core->dev, "Xilinx CSI2 Rx Subsystem Soft Reset Timeout!\n");
       return -ETIME;
   }

   Timeout--; 
   udelay(1);
}

   xcsi2rxss_clr(core, XCSI_CCR_OFFSET, XCSI_CCR_SOFTRESET_MASK);
   printk("CSI2 after reset %x\n", xcsi2rxss_read(core, 0x28));

   return 0

}

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Registered: ‎11-09-2015

Re: MIPI CSI2 Reset

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Hi matthew.singer@elbitsystems-us.com 

What is the output of the printk? Does the code enter the while loop?

Are all the clocks active (dphy_clk, lite_aclk, video_aclk) in your design?


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Registered: ‎09-05-2019

Re: MIPI CSI2 Reset

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The printk output is (I added a printk for the register write):

[ 2.529750] CSI2 write 28 1
[ 2.529758] CSI2 before reset 1
[ 2.529764] CSI2 write 0 3
[ 2.529771] CSI2 CSR 0
[ 2.530089] CSI2 write 0 1
[ 2.530095] CSI2 after reset 1

All three clocks are tied together on a free running MMCM output

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Registered: ‎11-09-2015

Re: MIPI CSI2 Reset

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Hi matthew.singer@elbitsystems-us.com 

Ok. So here what I see it that the reset function completes (as you still got "CSI2 after reset") , so the CSR bit is set (in contrary of your first message).

So this is the first thing I was focusing on.

Now I need to do some test about the register 0x28 and see if I get the same behaviour (i.e. no clear on reset). If I can I will check with development if it is expected.

Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Registered: ‎09-05-2019

Re: MIPI CSI2 Reset

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I expected to see bit 0 in the CSR go to 1 and back to 0, but that is not happening.

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Registered: ‎11-09-2015

Re: MIPI CSI2 Reset

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HI matthew.singer@elbitsystems-us.com 

Yes sorry from my understanding the CCR was not going to 1 (thus the reset was not happening).

I need to try the same test as you do and then discuss with development if the register 0x28 is affected by the reset. It might be a doc issue. The table should matbe say default value and not reset value


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Xilinx Employee
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Registered: ‎03-30-2016

Re: MIPI CSI2 Reset

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Hello matthew.singer@elbitsystems-us.com 

>I'm having an issue with the CSI2 receiver and my suspicion is that the block is not resetting properly.

Could you please elaborate more on the issue you have seen ?
Could you please share MIPI CSI-2 RX and MIPI D-PHY RX register dump also ?

>What I found is that CSR bit 0 is never set

Perhaps the reset is reset is already done , before you can read-back the CSR bit 0 (after you disabled Soft-Reset register).

My understanding is Soft reset does not reset register value.

Thanks & regards
Leo

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Registered: ‎11-09-2015

Re: MIPI CSI2 Reset

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HI matthew.singer@elbitsystems-us.com 

I was able to reproduce what you see in simulation:

  • A soft reset will not reset the value configured for the registers 0x20 and 0x28
  • However a hard reset will reset the value of the registers 0x20 and 0x28

I waiting for a confirmation from development but I think this is the expected behaviour of the core (i.e. configuration registers are not reset on a soft reset). If they confirm I will let you know and get the PG232 updated to clarify this.

Regards


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Registered: ‎09-05-2019

Re: MIPI CSI2 Reset

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As another test, we connected a GPIO to lite_aresetn and video_aresetn and held the line low.  In this case we assumed that the module would held in reset, but MIPI data flowed through it.

To further explain why I'm looking at reset as an issue...

We are using an On Semi camera connected to the CSI2 input.  Upon powerup, everything works fine.  Both devices are software reset, configured and streaming enabled.  Data flows.  But when streaming is stopped and the cycle repeated (minus the power being turned on), no data flows and and CL & DL status registers in the DPHY shows that the initialization is done, but that it in in low power mode (ie the register is an 8).

 

 

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Registered: ‎09-05-2019

Re: MIPI CSI2 Reset

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Is there any register that software does clear to verity that it is actually occuring?

 

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Registered: ‎11-09-2015

Re: MIPI CSI2 Reset

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HI matthew.singer@elbitsystems-us.com 


Is there any register that software does clear to verity that it is actually occuring?


The core status register should be cleared. But this is not a test you can do just by writting in the register as it is read only. You need to run the core.

As another test, we connected a GPIO to lite_aresetn and video_aresetn and held the line low.  In this case we assumed that the module would held in reset, but MIPI data flowed through it.

Can you explain what signals you look at to said that the data flows?


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Re: MIPI CSI2 Reset

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This is under linux so running a gstreamer pipeline 

gst-launch-1.0 -e v4l2src device=/dev/video0 do-timestamp=true io-mode=5 ! "video/x-raw, framerate=(fraction)30/1, width=(int)1920, height=(int)1080" ! kmssink bus-id=fd4a0000.zynqmp-display fullscreen-overlay=1 sync=false

The 2nd time this is run,  I see CSI2 driver go thru its reset routine, then the camera goes thru its reset and turns its streaming on, but the CSI2 never comes out of low speed mode.

As as test, when run the first time, I went into the camera driver and when it starts to stream, have it reset again and start to stream again and verify it is sending data, so I'm pretty sure its on the CSI2 side.

 

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Xilinx Employee
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Registered: ‎03-30-2016

Re: MIPI CSI2 Reset

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Hello matthew.singer@elbitsystems-us.com 

COuld you please share your MIPI CSI-2 RX and MIPI D-PHY register dump ?
For both : when everything works fine after power-up and when the issue occurs after second initialization.

Regards
Leo

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Re: MIPI CSI2 Reset

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When working:

[ 29.052199] CSI2 reg 0 1
[ 29.058416] CSI2 reg 4 1b
[ 29.064695] CSI2 reg 10 c6000000
[ 29.071580] CSI2 reg 20 1
[ 29.077819] CSI2 reg 24 20000
[ 29.084388] CSI2 reg 28 c03dffff
[ 29.091214] CSI2 reg 30 0
[ 29.097392] CSI2 reg 3c 0
[ 29.103546] CSI2 reg 40 0
[ 29.109658] CSI2 reg 44 0
[ 29.115734] CSI2 reg 48 0
[ 29.121779] CSI2 reg 4c 0
[ 29.127780] DPhyReg 10000 2
[ 29.133950] DPhyReg 10004 0
[ 29.140095] DPhyReg 10008 186a0
[ 29.146561] DPhyReg 10010 0
[ 29.152655] DPhyReg 10014 0
[ 29.158707] DPhyReg 10018 9
[ 29.164727] DPhyReg 1001c c6840008
[ 29.171360] DPhyReg 10020 c6840008
[ 29.177948] DPhyReg 10024 c6840008
[ 29.184496] DPhyReg 10028 c6840008
[ 29.191016] DPhyReg 10030 8f
[ 29.196983] DPhyReg 10048 8f
[ 29.202915] DPhyReg 1004c 8f
[ 29.208815] DPhyReg 10050 8f
[ 29.214681] DPhyReg 10054 8f

 

When not..

[ 120.702245] CSI2 reg 0 1
[ 120.707496] CSI2 reg 4 1b
[ 120.712807] CSI2 reg 10 0
[ 120.718087] CSI2 reg 20 1
[ 120.723329] CSI2 reg 24 0
[ 120.728540] CSI2 reg 28 c03dffff
[ 120.734356] CSI2 reg 30 0
[ 120.739553] CSI2 reg 3c 0
[ 120.744721] CSI2 reg 40 0
[ 120.749879] CSI2 reg 44 0
[ 120.755004] CSI2 reg 48 0
[ 120.760120] CSI2 reg 4c 0
[ 120.765248] DPhyReg 10000 2
[ 120.770575] DPhyReg 10004 0
[ 120.775867] DPhyReg 10008 186a0
[ 120.781524] DPhyReg 10010 0
[ 120.786816] DPhyReg 10014 0
[ 120.792091] DPhyReg 10018 8
[ 120.797363] DPhyReg 1001c 8
[ 120.802613] DPhyReg 10020 8
[ 120.807856] DPhyReg 10024 8
[ 120.813092] DPhyReg 10028 8
[ 120.818330] DPhyReg 10030 8f
[ 120.823660] DPhyReg 10048 8f
[ 120.828993] DPhyReg 1004c 8f
[ 120.834318] DPhyReg 10050 8f
[ 120.839635] DPhyReg 10054 8f

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Xilinx Employee
Xilinx Employee
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Registered: ‎03-30-2016

Re: MIPI CSI2 Reset

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Hello matthew.singer@elbitsystems-us.com 

Thanks for sharing your MIPI register dump.
I can see that nothing wrong with MIPI IPs register value on both cases.
It seems that your sensor stopped sending data, so the D-PHY packet counter for all lane are not increasing.

reg_comp.png

Regards
Leo

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Registered: ‎09-05-2019

Re: MIPI CSI2 Reset

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Scoped MIPI_CLK and MIPI_D0 and put a light into the camera.  Can see the data lines changing the same way following the light source when it working and the 2nd run where the CSI2/ DPHY is not passing data

 

 

 

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Xilinx Employee
Xilinx Employee
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Registered: ‎03-30-2016

Re: MIPI CSI2 Reset

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Hello matthew.singer@elbitsystems-us.com 

Thank you for confirming the sensor output.

>Scoped MIPI_CLK and MIPI_D0 and put a light into the camera. Can see the data lines changing the same way following the light source when it working and the 2nd run where the CSI2/ DPHY is not passing data

Okay, if you can ensure that your sensor is sending data correctly.
I am suspecting MIPI IP is under reset or input clocks are stopped, since packet counter is not incrementing.


1. Is video_aresetn is "1" or "0" ?
   (I can see from your previous post that you control video_aresetn from GPIO ).
2. Do you have multiple MIPI IP implemented on the same HP I/O bank ? Could you please share your configuration (,xci) for each instances ?  (Perhaps you are using a slave IP , while your master MIPI IP is disabled. )

Regards
Leo

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Registered: ‎09-05-2019

Re: MIPI CSI2 Reset

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  1. video_aresetn is connected to an AXI GPIO controller, bit 1, with default value of 0.
  2. There is only 1 MIPI CSI-2 Rx Subsystem in the entire design.  There is only 1 MIPI interface in the entire design.  The XCI file is attached.

 

Input clock of 200MHz for lite_aclk, dphy_clk_200M, and video_aclk is free-running with no clock gating present.

 

File renamed to .xml as it wouldnt let me attach it as .xci

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Xilinx Employee
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Registered: ‎03-30-2016

Re: MIPI CSI2 Reset

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Hello matthew.singer@elbitsystems-us.com 

I confirmed your XCI file , and I have one concern.
MATT_MIPI_CSI2_RX_XCI.png

Using above setting, you should use video_aclk with clock frequency 240MHz or higher. (See PG232 Chapter3 Clocking Section)
If you are using 200MHz right now, could you please  fix ?

Regards
Leo

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Re: MIPI CSI2 Reset

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After changing that, no frames flow. 

CONTROL register is 2

DPHY CL_STATUS and DL_STATUS are 0x8. 

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Xilinx Employee
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Re: MIPI CSI2 Reset

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Hello matthew.singer@elbitsystems-us.com 

I was asking to test 240 MHz for video_aclk, since PG232 Chapter3 suggested that
PG232_video_aclk.png

video_aclk2 = 1200 x 4 / 10 / 2 = 240 MHz (or higher frequency )

 

So my understanding is :
after clock modification, video_aclk should be 240MHz, while dphy_clk_200M and lite_aclk still use 200MHz.

MIPI_RX_BEFORE_AFTER_CLOCK_MODIFICATION.png

Using this clock modification , packet does not flow on the first reset ? ( Packet counter is fixed at zero ? )
Or did you connect 240 MHz for dphy_clk_200M also ?

Regards
Leo

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Registered: ‎09-05-2019

Re: MIPI CSI2 Reset

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It is setup like your picture

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Xilinx Employee
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Re: MIPI CSI2 Reset

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Hello matthew.singer@elbitsystems-us.com 


1. There is a possibility that MIPI D-PHY RX IP is not reset corretly

2. To confirm this, is it possible to modify the device tree by removing “xlnx,dphy-present” (so MIPI D-PHY register will keep untouch),
    and run the test again?

    # Could you please double check if the number of lanes set in the MIPI CSI2 Rx IP in 1st and 2nd run is the same ?

    # Also check if all MIPI CSI2 Rx registers are having same value during after 1st and 2nd call to xcsi2rxss_start_stream()

         Matt_to_modify_device_tree.png

Regards
Leo

@bpatil, @karnanl

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Registered: ‎09-05-2019

Re: MIPI CSI2 Reset

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Bingo!

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Xilinx Employee
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Re: MIPI CSI2 Reset

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Hello

Great ! Thanks for the update.

IMO, enabling/disabling D-PHY is not necessary when stop/re-start streaming data. I will give this feedback to our Linux Driver team.

 

Thanks & regards
Leo

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Registered: ‎09-05-2019

Re: MIPI CSI2 Reset

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Thanks Leo.  Appreciate the help.