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Contributor
Contributor
2,208 Views
Registered: ‎12-19-2017

MIPI D-PHY CSI-2 receiver change line rate

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We want to implment sensor tester based on (D-PHY IC + KINTEX-7) with XILINX MIPI CSI-2 receiver subsystem.

When we study PG232 https://www.xilinx.com/support/documentation/ip_documentation/mipi_csi2_rx_subsystem/v3_0/pg232-mipi-csi2-rx.pdf

 

There is no line rate register.

 

So if we are setting the line rate in IP wizard to 1500Mbps.  Can it receives line rate  1200Mbps on 1500Mbps setting?

 

Or we have to  using diffrent bitstream?

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Xilinx Employee
Xilinx Employee
3,180 Views
Registered: ‎03-30-2016

Re: MIPI D-PHY CSI-2 receiver change line rate

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@sychi2014  Also one more thing to consider is Global operation timing parameter as described in the MIPI spec.

Those parameters has min/max spec which many of them is defined as UI. ( min/max depends on the TX/RX line rate)

So, It would be complicated to check whether expected value of Global operation timing for MIPI D-PHY RX IP (that set as 1500Mbps) can be met by sensor that is set as 500Mbps. (and vice-versa)

So, keep the same line-rate on TX/RX is a wise choice. 

 

Thanks & regards
Leo

 

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Xilinx Employee
Xilinx Employee
2,182 Views
Registered: ‎03-30-2016

Re: MIPI D-PHY CSI-2 receiver change line rate

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Hello !

 

> There is no line rate register.

 

Yes your understanding is correct.

 

Our MIPI does not support dynamic line rate change. Please check on PG202.

 

> So if we are setting the line rate in IP wizard to 1500Mbps.  Can it receives line rate  1200Mbps on 1500Mbps setting?

 

It may work, so you can use it on testing purpose.

But I do recommend to use different bitstream on different line-rate as suggested by PG202.

Especially if you want to use it on production.

 

BTW, if you are on the planning phase , I would like to recomended using UltraScale+ device,

Since we have I/O with native MIPI D-PHY support and many customer already use it on their product. 

 

 

Best regards
Leo

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Contributor
Contributor
2,167 Views
Registered: ‎12-19-2017

Re: MIPI D-PHY CSI-2 receiver change line rate

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Hi Leo,

 

Thanks for your reply.

 

It stii confused  me with the line rate change issue.

 

I try to see the block diagram in output MIPI CSI subsystem IP & reference design on ZCU102.

The DPHY de-serialized data by source synchronous CLOCK lane and the 200MHz core_clk to handle control logic.

Then  DPHY transmit data to MIPI CSI controller with input clock divide 8 (For example, 1200Mbps line rate, clock path divide by 8 to 150MHz)  

 

Why can't we receive diffrent MIPI sensor with the same architecture if we do STA under 1500Mbps line rate(187.5MHz clock)? 

 

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Xilinx Employee
Xilinx Employee
2,136 Views
Registered: ‎03-30-2016

Re: MIPI D-PHY CSI-2 receiver change line rate

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@sychi2014 

If MIPI IP is a single clock domain, I think no problem will occured if you constraint the IP with 1500Mbps, and use it with a slower clock. But on general this cases cannot be applied on multi-clock domain, since phase relation between clock may needed depends on logic implementation .

Best regards
Leo

Contributor
Contributor
2,125 Views
Registered: ‎12-19-2017

Re: MIPI D-PHY CSI-2 receiver change line rate

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Thank you again @karnanl

 

As you said there are multiple clock domain.

I trace MIPI CSI-2 Rx subsystem IP and find out the timing constaints.

It's only create clock constraint. No set_max_delay/set_min_delay for STA.

So I think the IP build with CDC design. Is there any phase issue for this?

 

Or anything I misunderstanding for this case?

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Xilinx Employee
Xilinx Employee
2,084 Views
Registered: ‎03-30-2016

Re: MIPI D-PHY CSI-2 receiver change line rate

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Hello @sychi2014

Pardon me for missing your reply.

 

As far as I know there is no CDC issue in MIPI RX IP. 

You can check your own design by using the following command to make sure the timing is clean. 

- report_timing_summary -report_unconstrained  = to check unconstrained path 

- report_clock_interaction  = to check  Timed(Unsafe) path 

Xilinx Employee
Xilinx Employee
3,181 Views
Registered: ‎03-30-2016

Re: MIPI D-PHY CSI-2 receiver change line rate

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@sychi2014  Also one more thing to consider is Global operation timing parameter as described in the MIPI spec.

Those parameters has min/max spec which many of them is defined as UI. ( min/max depends on the TX/RX line rate)

So, It would be complicated to check whether expected value of Global operation timing for MIPI D-PHY RX IP (that set as 1500Mbps) can be met by sensor that is set as 500Mbps. (and vice-versa)

So, keep the same line-rate on TX/RX is a wise choice. 

 

Thanks & regards
Leo

 

Contributor
Contributor
2,043 Views
Registered: ‎12-19-2017

Re: MIPI D-PHY CSI-2 receiver change line rate

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Hi @karnanl

 

Thanks for you explanation.

 

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Moderator
Moderator
2,034 Views
Registered: ‎11-09-2015

Re: MIPI D-PHY CSI-2 receiver change line rate

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HI @sychi2014,

 

If the responses for Leo @karnanl are enough for you, please kindly mark a reply as accepted solution to close the topic.

 

Thanks,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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Adventurer
Adventurer
1,403 Views
Registered: ‎01-19-2018

Re: MIPI D-PHY CSI-2 receiver change line rate

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Hello,

differences of between D-Phy version 1.1 and version 1.2. if Tx is 1.1 and Rx 1.2 revisions what additional configurations are required?

--Thanks.
 
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Moderator
Moderator
759 Views
Registered: ‎11-09-2015

Re: MIPI D-PHY CSI-2 receiver change line rate

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Hi @daram123,

 

This is a different question and this topic was not created by you.

 

As per the guidelines for the video board:

 

4. Do not post a question on someone else's topic. Create a new topic if you have an issue. It might not be the same issue

 

I am closing this topic for new replies. Please create a new topic for your question.

 

Thank you for you understanding


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**