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Visitor tommymc
Visitor
727 Views
Registered: ‎06-05-2018

MIPI D-PHY DSI Frame sync options

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I am using MIPI DSI Tx Subsystem v2.0 with AXI VDMA.

 

According to page 14 of the product guide, s_axis_tuser (Start of Frame) is not used in the core so how do I keep frame sync with the DMA frame transfers?

 

The MIPI Tx SS core keeps its own video timing but without any feedback from the core how can you know when you have lost frame sync or even establish the start of the first frame from the VDMA frame buffer?

 

Any insight would be greatly appreciated!

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Visitor tommymc
Visitor
618 Views
Registered: ‎06-05-2018

Re: MIPI D-PHY DSI Frame sync options

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So after a few days of frustration I finally found the issue.

 

The hardware was behaving differently depending on which order the MIPI DSI library functions were called.

The MIPI core was not getting configured/reset properly to synchronize to the start of new frames.

This is because there is only one global in the library code that holds the core driver data:

(In file xdsitxss.c)

 

/**************************** Variable Definitions ***********************************/

XDsiTxSs_SubCores DsiTxSsSubCores; /**< Define Driver instance of all sub-core included in the design */

 

I am running two MIPI panels, so I when I initialized the second interface the first core never worked properly because the global data structure was stepped on, and when calls were made to start the first interface again it would corrupt the data in the second driver instance, etc.

 

I modified the library code to handle two separate interfaces and that fixed the issue.

 

 

3 Replies
Moderator
Moderator
664 Views
Registered: ‎10-04-2017

Re: MIPI D-PHY DSI Frame sync options

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Hi @tommymc,

 

 

According to page 14 of the product guide, s_axis_tuser (Start of Frame) is not used in the core so how do I keep frame sync with the DMA frame transfers?

When using AXI-S you do not have to sync transfers, in this case, you only need to make sure that you are providing the correct amount of pixel data to the TX core and that the core is initialized before the upstream cores. This way you are not running into a buffer full or underflow situation.

 

From PG238:

"Because the MIPI protocol does not allow throttling on the output interface, the module
connected to the input of this subsystem should have sufficient bandwidth to pump the
pixel data at the required rate."

 

 

The MIPI Tx SS core keeps its own video timing but without any feedback from the core how can you know when you have lost frame sync or even establish the start of the first frame from the VDMA frame buffer?

AXI-S helps us here as well. Because we are not using native mode, we only transfer pixel data. This means that the first data sent to the core is the start of the first frame. This is why you do not start your video stream (AXI-S interface) until you initialize the TX SubSystem, this way you ensure that no data is dropped and that the first data is the start of the first frame.

 

Another way to look at this is to switch from a Sync point of view to an underrun/buffer full point of view. If you have underrun or buffer full, you are either not sending enough data, too much data or there is an issue with the link and data is not being sent. In these cases, you will need to check your design to verify the link and the data rate into the core.

 

For an example of a working system, please see chapter 5 of PG232.

 

-Sam

 

 

 

Don't forget to reply, kudo, and accept as solution.

Xilinx Video Design Hub
Visitor tommymc
Visitor
619 Views
Registered: ‎06-05-2018

Re: MIPI D-PHY DSI Frame sync options

Jump to solution

So after a few days of frustration I finally found the issue.

 

The hardware was behaving differently depending on which order the MIPI DSI library functions were called.

The MIPI core was not getting configured/reset properly to synchronize to the start of new frames.

This is because there is only one global in the library code that holds the core driver data:

(In file xdsitxss.c)

 

/**************************** Variable Definitions ***********************************/

XDsiTxSs_SubCores DsiTxSsSubCores; /**< Define Driver instance of all sub-core included in the design */

 

I am running two MIPI panels, so I when I initialized the second interface the first core never worked properly because the global data structure was stepped on, and when calls were made to start the first interface again it would corrupt the data in the second driver instance, etc.

 

I modified the library code to handle two separate interfaces and that fixed the issue.

 

 

Moderator
Moderator
589 Views
Registered: ‎10-04-2017

Re: MIPI D-PHY DSI Frame sync options

Jump to solution

Hi @tommymc,

 

Good job debugging the issue.

I have pushed your feedback to the driver team.

 

Thank you,

Sam

Don't forget to reply, kudo, and accept as solution.

Xilinx Video Design Hub