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Visitor achafe
Visitor
170 Views

MIPI D-PHY Example Design Hardware Test

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Hello,

I have been having issues implementing the MIPI DSI Core. In an attempt to test the assigned pins and complete a MIPI loopback I loaded the MIPI DPHY Example design as described in PG202 Ch 5. This document states that the "The top module instantiates all components of the core and example design that are needed to implement the design in hardware" however when i open the example design there is no top level, it only builds the TX half of the design. I tried creating my own top level but then discovered that the RX modules are simulation only. 

Is there any way for me to test the MIPI D-PHY output in a loopback on a board?

 

 

Amy

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Xilinx Employee
Xilinx Employee
139 Views

Re: MIPI D-PHY Example Design Hardware Test

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Hello @achafe

 

(a) Your understanding is correct, if you generate MIPI D-PHY TX IP and generate the Example Design,

It consisted of FRM_GEN + MIPI D-PHY TX IP only. ( and it is similar for MIPI D-PHY RX Example Design too )

The main purpose of this D-PHY Example design is to generate a simple testbench for user quick reference to check the behavior of D-PHY TX/RX IP )

 

(b)  The FRM_GEN and FRM_CHK modules from the Example design are only a sample of stimulus for the D-PHY IP, It will not be so useful in real HW test.

If you want to do pin assignment check for your project, generate example design, add the pin-assignment constraint and do implementation will do the job.

If you are looking for a working Example design, please check PG232 Chapter5. This Example design also using MIPI DSI TX IP. (Please use Vivado 2018.1 or 2018.2)

Example_Des.png

 

Thanks & regards

Leo

 

2 Replies
Xilinx Employee
Xilinx Employee
140 Views

Re: MIPI D-PHY Example Design Hardware Test

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Hello @achafe

 

(a) Your understanding is correct, if you generate MIPI D-PHY TX IP and generate the Example Design,

It consisted of FRM_GEN + MIPI D-PHY TX IP only. ( and it is similar for MIPI D-PHY RX Example Design too )

The main purpose of this D-PHY Example design is to generate a simple testbench for user quick reference to check the behavior of D-PHY TX/RX IP )

 

(b)  The FRM_GEN and FRM_CHK modules from the Example design are only a sample of stimulus for the D-PHY IP, It will not be so useful in real HW test.

If you want to do pin assignment check for your project, generate example design, add the pin-assignment constraint and do implementation will do the job.

If you are looking for a working Example design, please check PG232 Chapter5. This Example design also using MIPI DSI TX IP. (Please use Vivado 2018.1 or 2018.2)

Example_Des.png

 

Thanks & regards

Leo

 

Moderator
Moderator
96 Views

Re: MIPI D-PHY Example Design Hardware Test

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Hi @achafe,

 

Is everything clear for you? Was the reply from @karnanl enough for you?

 

If your question is answered or your issue is solved, please kindly mark the response which helped as solution (click on "Accept as solution" button below the reply)

If this is not solved/answered, please reply in the topic giving more information on your current status.

Thanks and Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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