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Visitor zhxwu
Registered: ‎08-08-2019

MIPI D-PHY IP simulation issue

I instantiated a MIPI D-PHY IP in vivado and configured this DPHY as a 4 lane RX dphy. Then I used a clk_wizard to generate the core_clk that dphy used and an ILA to debug the waveform. So, the whole design looks like a simple rx dphy. Then I just simply systhesis and implementation the design with no setup/hold violation. We plan to use this dphy FPGA board connected with a camera sensor daughter board and a CSI controller board. In the first version, when the whole environment was ready. The PPI signals seen from the ILA debug waveform seems not correct. As we can seen from the bolow screenshot image ppi-boxing.png, data lane0 and data lane2 will set the errsoths to high for 1 rxbyteclkhs, before rxdatahs was generated. but data lane1 and data lane3 not. Does this waveform looks correct? Another question about the DPHY, I want to simulate the whole design before synthsis, but DPHY has to many PPI signals and it is diffcult for me to write a testbench to drive the whole design. I would like to know is there any avaliable testbench that XILINX provided. And we can use this testbench to stimulus all the related signals in my design.
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Xilinx Employee
Xilinx Employee
Registered: ‎03-30-2016

Re: MIPI D-PHY IP simulation issue

Hello @zhxwu

Xilinx do have an MIPI Example Design with simulation testbench. (Please read PG202 Chapter 5 )

Could you please start from this Example Design ?
Please let me know if you have difficulity runnig the simulation.

Thanks & regards

-- MIPI is a Video IP. For MIPI related question please post on https://forums.xilinx.com/t5/Video/bd-p/DSPTOOL

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Registered: ‎11-21-2018

Re: MIPI D-PHY IP simulation issue


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