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Visitor jyingling
Visitor
718 Views
Registered: ‎07-26-2018

MIPI D-PHY RX SOT incorrect

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Hello,

 

We are using a Zync xc7z030sbg485-1 part with Vivado 2018.2 utilizing MIPI D-PHY v4.1 as an RX. I have a MIPI transmitter external the the Zync part.

 

The external circuitry is setup as in XAPP894 for the fully compliant solution and the input signals look good with oscope and the 0xb8 sync byte is visible going into the zync soc. The MIPI D-PHY is outputting a rxbyteclkhs of 112 MHz as expected (DDR differential input clock is running at 896 Mbits/s per lane (448Mhz but at ddr). The D-PHY is also setting the rxactivehs signals high to indicate that a SOT event was detected on all 4 data lanes. The SOT error bits are all 0 indicating no errors were detected. 


However, when looking at the deserialized output of the D-PHY RX I do not see the expected SOT start byte of 0xB8. I instead see different byte values on each data lane preceded by a string of zeros as expected.

 

My question is whether or not the D-PHY RX should output 0xB8 as the first byte on each data lane when coming into high speed mode or is the 0xB8 never sent out but only detected and the first valid byte out of the deserialzer is the byte immediately after the 0xB8?

 

I'm trying to decode the MIPI data stream and need to parse it but I'm not having confidence in the data because the sync byte is not seen. 

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Xilinx Employee
Xilinx Employee
855 Views
Registered: ‎12-02-2009

Re: MIPI D-PHY RX SOT incorrect

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0xB8 (sync byte) will be never be part of D-PHY RX output. D-PHY RX has simulation support and can be confirmed with simulation.

5 Replies
Xilinx Employee
Xilinx Employee
856 Views
Registered: ‎12-02-2009

Re: MIPI D-PHY RX SOT incorrect

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0xB8 (sync byte) will be never be part of D-PHY RX output. D-PHY RX has simulation support and can be confirmed with simulation.

Visitor jyingling
Visitor
681 Views
Registered: ‎07-26-2018

Re: MIPI D-PHY RX SOT incorrect

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Thank you for the reply.

 

I'll take another look at the MIPI D-PHY example project to try and confirm this. 

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Xilinx Employee
Xilinx Employee
657 Views
Registered: ‎03-30-2016

Re: MIPI D-PHY RX SOT incorrect

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Hello @jyingling

>However, when looking at the deserialized output of the D-PHY RX I do not see the expected SOT start byte of 0xB8.
>I instead see different byte values on each data lane preceded by a string of zeros as expected.

Please let me confirm what you are trying to do here.

You probed rx_dl*_s_dp[7:0] from ISERDES2 but cannot found find any 0xB8 on all data lanes.
Is my understanding correct ?

If this is the case then, I think that is possible. Becase you may see SoT symbol shifted, so it is not displayed as 0xB8 on the data lanes.
If you can share you ILA capture, I can help you to check the waveform.

Best regards
Leo

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Visitor jyingling
Visitor
646 Views
Registered: ‎07-26-2018

Re: MIPI D-PHY RX SOT incorrect

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I think the original answer was correct. It looks like the 0xB8 sync byte never shows up on the output. As you can see in the capture the dl*_rxsynchs outputs all go high (indicating a valid SoT was detected). So I'm assuming my data is good after the rxsynchs goes high.

 

To answer your question I am probing dl*_rxdatahs(7:0) (the output of the MIPI_dphy IP). But are you saying if I probe directly the output of ISERDES I would probably see the 0xB8? However, the MIPI_dphy bit aligns the data by looking for the 0xB8 sync byte and then outputs the packet data after that.

 

What I'm seeing in the capture looks to me like valid MIPI high speed packet data.

mipi_capture.PNG
Xilinx Employee
Xilinx Employee
637 Views
Registered: ‎03-30-2016

Re: MIPI D-PHY RX SOT incorrect

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@jyingling

 

> But are you saying if I probe directly the output of ISERDES I would probably see the 0xB8?

 

Yes.

But byte aligned may not be correct so you will sometimes see 0xB8 symbol shifted on ISERDES output.

 

Best regards

Leo

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