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Contributor
Contributor
552 Views
Registered: ‎01-03-2019

MIPI_DPHY RX SIM_MODEL behavior error

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problem:

Mipi-dphy rx: 1 diff clk;4 diff data.

When diff data rate is 185.65Mbpsper laneDDR, Mipi-dphy RX sim model can recive data correct; When diff data rate is 594Mbpsper laneDDR, Mipi-dphy RX sim model recive data error,cannot recongnize frame header fail(data package error) ;

What’s problem

ZCU 102

Vivado vision2017.3

MIPI-DPH vision4.0

MIPI-DPHY config

1.png2.png

sim_model file:

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1 Solution

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Xilinx Employee
Xilinx Employee
413 Views
Registered: ‎03-30-2016

Re: MIPI_DPHY RX SIM_MODEL behavior error

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Hello @taylor91 

1. This issue will affect both sim and HW.
2. Looking at your sim error message
    It seems that your simulation including Xilinx protected modules (secureip) with .vp extension,  I believe the module contents were non-accessible for 3rd party simulator directly.

3. Vivado support 3rd party simulator using , it can be run from Vivado window.
Please see also UG900 Chapter 1~3  https://www.xilinx.com/support/documentation/sw_manuals/xilinx2019_1/ug900-vivado-logic-simulation.pdf  
It mentioned basic step how to launch simulation using Vivado GUI. Suggest you to follow this for first time trial.

It would be better if you can start simulation from Example Design.
Vivado will generate a script to launch the simulation,  so you can check the script to find if you have missed some important file.
Please note that we should pre-compile simulation libraries for 3rd party simulator.
Usually if there is no compiled simulation libraries available, simulation will not run.

 

Thanks & regards
Leo

14 Replies
Xilinx Employee
Xilinx Employee
521 Views
Registered: ‎03-30-2016

Re: MIPI_DPHY RX SIM_MODEL behavior error

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Hello @taylor91 

Are you using the same IP setting (Line-rate 1000Mbps) to receive multiple line-rate usecase ( for ex: 594Mbps and 185.65 Mbps ) ??

If, Yes.
This is not a  supported usecase.

Hope this helps.

Thanks
Leo

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Contributor
Contributor
505 Views
Registered: ‎01-03-2019

Re: MIPI_DPHY RX SIM_MODEL behavior error

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i change  the  data rate  to 594Mbps,also  has  the   problem.sim  include cell:

IMG_20190905_210338.jpg

sim  wave(cannot  get  frame  header):

IMG_20190905_210407.jpg

 

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Xilinx Employee
Xilinx Employee
496 Views
Registered: ‎03-30-2016

Re: MIPI_DPHY RX SIM_MODEL behavior error

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Hello @taylor91 

This is a MIPI D-PHY IP bug , and already fixed in 2018.3.
Could you please migrate to Vivado 2018.3 or later version, and redo the simulation ?

Thanks
Leo

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Contributor
Contributor
479 Views
Registered: ‎01-03-2019

Re: MIPI_DPHY RX SIM_MODEL behavior error

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Just a sim bug? if i use this dphy (data rate config 594 mbps to receive sensor data ) test in ZCU 102 board ,is any problem?
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Contributor
Contributor
443 Views
Registered: ‎01-03-2019

Re: MIPI_DPHY RX SIM_MODEL behavior error

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i use vivado 2019.1 generate mipi_dphy RX  ip (data rate config 594Mbps). When I use vcs  sim , complie error. 

info as follow:

1.jpg

MIPI sim file as follow:4.jpg

refer solution:https://www.xilinx.com/support/answers/56390.html.

vcs vision: 2015.9

what's the problem?lib less?

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Xilinx Employee
Xilinx Employee
414 Views
Registered: ‎03-30-2016

Re: MIPI_DPHY RX SIM_MODEL behavior error

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Hello @taylor91 

1. This issue will affect both sim and HW.
2. Looking at your sim error message
    It seems that your simulation including Xilinx protected modules (secureip) with .vp extension,  I believe the module contents were non-accessible for 3rd party simulator directly.

3. Vivado support 3rd party simulator using , it can be run from Vivado window.
Please see also UG900 Chapter 1~3  https://www.xilinx.com/support/documentation/sw_manuals/xilinx2019_1/ug900-vivado-logic-simulation.pdf  
It mentioned basic step how to launch simulation using Vivado GUI. Suggest you to follow this for first time trial.

It would be better if you can start simulation from Example Design.
Vivado will generate a script to launch the simulation,  so you can check the script to find if you have missed some important file.
Please note that we should pre-compile simulation libraries for 3rd party simulator.
Usually if there is no compiled simulation libraries available, simulation will not run.

 

Thanks & regards
Leo

Scholar watari
Scholar
404 Views
Registered: ‎06-16-2013

Re: MIPI_DPHY RX SIM_MODEL behavior error

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Hi @taylor91 

 

I'm not familiar with VCS and MIPI.

But it seems tool version issue.

 

Wolud you refer this document and use supported version ?

 

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2019_1/ug900-vivado-logic-simulation.pdf

 

Best regards,

Contributor
Contributor
356 Views
Registered: ‎01-03-2019

Re: MIPI_DPHY RX SIM_MODEL behavior error

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you are right,it is a version issue.

vivado 2019.1 require sim tool version  as follow:

1.jpg

 

Contributor
Contributor
350 Views
Registered: ‎01-03-2019

Re: MIPI_DPHY RX SIM_MODEL behavior error

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Thanks   for  your reply  again .

In fact, i include xilinx  .vp files.They are encrypted files. Only matched  sim tool  version can decrypt(run from Vivado window also has the rule) those files .

https://forums.xilinx.com/t5/Simulation-and-Verification/Vivado2018-1-IP-simulation-files-decryption-failed-with-VCS-MX/m-p/868442#M22666

i must update sim tools to use the sim_model.

 

Contributor
Contributor
329 Views
Registered: ‎01-03-2019

Re: MIPI_DPHY RX SIM_MODEL behavior error

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i'm sorry  for touble you again.

i use vivado 2019.1 generate a dphy config as follows:

 11.jpg

input data rate 594 Mbps (DDR), sim also can't  get frame header(test in ZCU102 also has the problem),sim wave as follows:

22.png

4 lanes RXSYNCHS  effective  not in same time.

sim file as follows(tools VCS O-2018.09) :

21.jpgsim_model as follows.

looking forward your reply.

 

 

 

  

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Contributor
Contributor
323 Views
Registered: ‎01-03-2019

Re: MIPI_DPHY RX SIM_MODEL behavior error

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@karnanl     the problem as above.  

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Xilinx Employee
Xilinx Employee
292 Views
Registered: ‎03-30-2016

Re: MIPI_DPHY RX SIM_MODEL behavior error

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Hello @taylor91 

 

Could you please share the following signals from your sim ??

rxdatahs

rxvalidhs

rxactivehs

rxsynchs

soterrhs

sotsyncerrhs

cl_rxactivehs

dl_rx_state

dl_en_hs_rx_term

lp_00_r

lp_01_r

lp_10_r

lp_11_r


Thanks & regards
Leo

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Contributor
Contributor
279 Views
Registered: ‎01-03-2019

Re: MIPI_DPHY RX SIM_MODEL behavior error

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Hello @karnanl,

sim error has  been solved. The reason why dphy can't get  frame header is that sensor model  function doesn't meet mipi Specification.

This  is mipi Specification  require timing in HS-MODE:

MIPI_PRO.jpg

this is our sensor model output(the timing too short),and  dl<n>_ errsoths signal effective:

SOT.jpg

Then I change the sensor model ,dphy can capture correct data.

Thanks for your help >_<

 

Thanks & regards
taylor91 

 

 

 

 

 

 

Xilinx Employee
Xilinx Employee
261 Views
Registered: ‎03-30-2016

Re: MIPI_DPHY RX SIM_MODEL behavior error

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Hello @taylor91 

I've also seen some MIPI IP VIP model behavior from major company does not compliant with MIPID-PHY spec.
Thank you very much for debugging this and sorry for my late response.

Could you please close this thread, so other community user can learn from your experience.

Thanks & regards
Leo

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