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Visitor zhxwu
Visitor
435 Views
Registered: ‎08-08-2019

MIPI DPHY RX register issue

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Hi 

I have initiated a MIPI D-PHY IP as a RX in my vivado project. When I configured the DPHY ip, I didn't select the ENABLE AXI4-lite Register I/F, but recently we found that we need to modify the DPHY register  HS_SETTLE REGISTER to meet the requirment of host and slave HS_SETTLE time. Is there any other way to write this register without reconfigure the DPHY ip to generate AXI4 IF. 

My design was connected to a camera sensor to receivce the 4 lane differential serial signals and connect the output PPI interface signals to a CSI controller. If we need to reconfigure the DPHY ip to add AXI4 IF, is there any other register we may need to modify to meet the camera sensor's  timing requirment. 

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Moderator
Moderator
402 Views
Registered: ‎11-09-2015

Re: MIPI DPHY RX register issue

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HI @zhxwu 

As per the following topic, this is not recommended to modify the value of HS_SETTLE

https://forums.xilinx.com/t5/Video/MIPI-DPHY-configure-issue/m-p/1020460

With that said, it is possible to change the value without enabling the AXI4-Stream interface, using the properties window:

dphy.JPG

Regards


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**

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7 Replies
Moderator
Moderator
403 Views
Registered: ‎11-09-2015

Re: MIPI DPHY RX register issue

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HI @zhxwu 

As per the following topic, this is not recommended to modify the value of HS_SETTLE

https://forums.xilinx.com/t5/Video/MIPI-DPHY-configure-issue/m-p/1020460

With that said, it is possible to change the value without enabling the AXI4-Stream interface, using the properties window:

dphy.JPG

Regards


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**

View solution in original post

Visitor zhxwu
Visitor
380 Views
Registered: ‎08-08-2019

Re: MIPI DPHY RX register issue

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Hi Florent,

Thanks for your reply.

I didn't use the block design flow to build the vivado project. I just initiated all the ip in my top_design.v verilog file. So I could not find the Block Properties window shown in your screen shot. May I ask you how to open this Block Properties window if I didn't use the block design flow?

Moderator
Moderator
372 Views
Registered: ‎11-09-2015

Re: MIPI DPHY RX register issue

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HI @zhxwu 

The best way is by using the Block Design.

Without using the block design you would need the following steps:

  1. Reset the IP output products (right click on the IP > reset output products)
  2. Then enter the following command in the tcl console (you can change the value, 99 was just for my testing)
    set_property CONFIG.C_HS_SETTLE_NS 99 [get_ips mipi_dphy_0]
  3. Regenerate the IP output products

If you open the generated file mipi_dphy_0_c1.v generated under the core, you will see that the parameter C_HS_SETTLE_NS is updated

// HS_SETTLE timing parameter in ns
   // min is 85 + 6 UI
   // max is 145 + 10 UI
   parameter C_HS_SETTLE_NS = 99,

Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
Visitor zhxwu
Visitor
363 Views
Registered: ‎08-08-2019

Re: MIPI DPHY RX register issue

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Hi Florent,

My vivado design is not very complex, it's include a MIPI DPHY ip,  a ila debug ip and a clk wizard ip. I didn't use any PS side resources. So if I use the block design flow to build the whole project, I may not use the ZYNC Ultrascale ip. Is it correct that not use ZYNC Ultrascale ip in block design flow?

Moderator
Moderator
361 Views
Registered: ‎11-09-2015

Re: MIPI DPHY RX register issue

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HI @zhxwu 

Yes this is correct. You do not have to use any processor in the block design. So a Block design without Zynq or Microblaze is perfectly fine.

 


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
Moderator
Moderator
337 Views
Registered: ‎11-21-2018

Re: MIPI DPHY RX register issue

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@zhxwu 

If your question is answered or your issue is solved, please kindly mark the response which helped as solution (click on "Accept as solution" button below the reply).

 

If this is not solved/answered, please reply in the topic giving more information on your current status.

 

Thanks and Regards,

Aoife
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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Visitor zhxwu
Visitor
324 Views
Registered: ‎08-08-2019

Re: MIPI DPHY RX register issue

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Hi Florent, Thanks for your help. I have rebuild the whole design using Block Design flow and successfully generating the bitfile.
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