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Visitor zhxwu
Visitor
404 Views
Registered: ‎08-08-2019

MIPI DPHY configure issue

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Hi all,

I have some questions when congiuring MIPI DPHY IP and reading the pg202 document.

1. When I cofigure the DPHY IP as 4 lane RX, there is a configuration option called Line Rate(Mbps),what is the function of this cofiguration and what is the influence on DPHY when I set different Line Rate. 

2.In pg202 chapter3, there is a register HS_SETTLE. The default value of this register is 135+10UI. My question is what is the exact value of 1UI, how to caculate the value of 1UI. Does the Line Rate or the diff serial clk from camera sensor have any relationship with the caculation of 1UI value?

3.Does the Line Rate have any influence on HS_SETTLE time?

4.In pg202 Appx.B section DPHY Protocol Checks. There is description Ensure HS_SETTLE of D-PHY RX matches with the HS_PREPARE + HS_ZERO of DPHY TX. Could you please give me an explaination of this description? Does this description means we should modify the register HS__SETTLE in DPHY RX, or can we simply change the configurration of camera sensor to meet this requirment without modify DPHY register?

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Xilinx Employee
Xilinx Employee
274 Views
Registered: ‎03-30-2016

Re: MIPI DPHY configure issue

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Hello @zhxwu 

Thanks for the update.

2.When the DPHY RX terminal resistor couldn’t be enable, Why there is waveform in PPI interface?

Signal quality will degraded a lot, but IP might still recognize LP/HS data.
So, (especially) in lower line-rate usecase, MIPI D-PHY RX  might still output correct data on the PPI interface.

1.What configuration of DPHY may cause the MIPI HS RX termination resistor opening fail? 

You are using 2018.2 IP.  Please migrate to 2018.3 or please use "set_property DIFF_TERM_ADV" mentioned in the following AR.
https://www.xilinx.com/support/answers/71582.html. Could you please check and follow the suggestion.

How could we confirm the DPHY status is right or not?

We can have more discussion after you can confirm HW behaviour with AR#71582.
At first, I would like to see MIPI D-PHY register dump.

Regards
Leo

7 Replies
Xilinx Employee
Xilinx Employee
389 Views
Registered: ‎03-30-2016

Re: MIPI DPHY configure issue

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Hello @zhxwu 

1. Line Rate(Mbps) will set the expectation data rate for serial input signal in Mbps.
For example if your Camera/Sensor/Tx module sending 1000Mbps serial data, please set the samel Line-rate in MIPI CSI-2 RX Subsystem.

2.
(a) In most cases HS_SETTLE default setting works fine.
Unless your Camera/Sensor/Tx module does not follow "Global operation timing parameter" mentioned by MIPI D-PHY specification Table 14, please we do not recommend any modification on this register.
Xilinx MIPI CSI-2 RX compliant with MIPI D-PHY specification requirement.
(b) UI is Unit-Interval
If your TX is sending 1000Mbps serial signal , 1UI is 1ns
If your TX is sending 500Mbps serial signal , 1UI is 2ns, and so on.


3. Yes.

4. Please do not modify HS_SETTLE register setting if your system does not require any timing tuning.
Set the MIPI CSI-2 RX Line Rate to match your TX output.

Thanks & regards
Leo

Visitor zhxwu
Visitor
340 Views
Registered: ‎08-08-2019

Re: MIPI DPHY configure issue

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Hi Leo,

Thanks for your reply. 

we  still have some questions about DPHY configuration.

We have double check the P/N connection, Now the Sensor MIPI TLPX and prepare timing is meet MIPI spec, and we have try to adjust the prepare timing, but the DPHY HS RX termination resistor always couldn’t enable, but we still could get waveform at PPI interface, the output MIPI waveform of sensor is shown  below.

waveform1.jpg

When we add external 100 ohm resistor between Data P and Data N, Clock P and clock N, waveform is as shown below. 

waveform2.jpg

Questions:
⦁ What configuration of DPHY may cause the MIPI HS RX termination resistor opening fail? How could we confirm the DPHY status is right or not?
⦁ When the DPHY RX terminal resistor couldn’t be enable, Why there is waveform in PPI interface?

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Xilinx Employee
Xilinx Employee
321 Views
Registered: ‎03-30-2016

Re: MIPI DPHY configure issue

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Hello @zhxwu 

Thank you very much for the update. Sorry for my late response.

1. I do not have answer for your questions now.
    But I do agree that this behavior is not correct.
2. So, could you please confirm the following items ?

   (a) Are you using UltraScale+ device ? ( I assumed yes )
   (b) MIPI D-PHY I/O banks needs 1.2V supply. Could you please confirm this on your board ? (I mean by measuring the excact power-rail voltage level)
   (c) Are you using Vivado 2018.3 (or newer Vivado version)
   (d) To use an HP I/O bank with the MIPI_DPHY_DCI I/O standard, the VRP of the I/O bank needs to be connected to ground via a 240 ohm resistor.
   (e) if the VRP is nnot connected (NC). To use MIPI_DPHY_DCI on these banks, DCI Cascade must be used.
            "set_property DCI_CASCADE {slave_banks} [get_iobanks master_bank]"

Thanks & regards
Leo

Visitor zhxwu
Visitor
294 Views
Registered: ‎08-08-2019

Re: MIPI DPHY configure issue

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Hi Leo, Thanks for your reply. Here is the information you need to be confirmed. (a) Yes, I used xczu4eg-fbvb400-1-e. (b) Our board was bought from other company, They have already verified the whole csi+dphy subsystem on board before delivered. So I think all MIPI I/O bank is 1.2v. (c) No, my vivado is 2018.2. (d) It has been connected to ground via a resistor. And my question is still about the termination issue, Could you help me about this two questions below? 1.What configuration of DPHY may cause the MIPI HS RX termination resistor opening fail? How could we confirm the DPHY status is right or not? 2.When the DPHY RX terminal resistor couldn’t be enable, Why there is waveform in PPI interface?
Xilinx Employee
Xilinx Employee
275 Views
Registered: ‎03-30-2016

Re: MIPI DPHY configure issue

Jump to solution

Hello @zhxwu 

Thanks for the update.

2.When the DPHY RX terminal resistor couldn’t be enable, Why there is waveform in PPI interface?

Signal quality will degraded a lot, but IP might still recognize LP/HS data.
So, (especially) in lower line-rate usecase, MIPI D-PHY RX  might still output correct data on the PPI interface.

1.What configuration of DPHY may cause the MIPI HS RX termination resistor opening fail? 

You are using 2018.2 IP.  Please migrate to 2018.3 or please use "set_property DIFF_TERM_ADV" mentioned in the following AR.
https://www.xilinx.com/support/answers/71582.html. Could you please check and follow the suggestion.

How could we confirm the DPHY status is right or not?

We can have more discussion after you can confirm HW behaviour with AR#71582.
At first, I would like to see MIPI D-PHY register dump.

Regards
Leo

Visitor zhxwu
Visitor
236 Views
Registered: ‎08-08-2019

Re: MIPI DPHY configure issue

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Hi Leo, Many thanks for your help. I used the "set_property DIFF_TERM_ADV" constraint in the AR you mentioned. And now we can see the temination of diff serial port on our oscilloscope successfully.
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Xilinx Employee
Xilinx Employee
219 Views
Registered: ‎03-30-2016

Re: MIPI DPHY configure issue

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Hello @zhxwu 

Thank you for debugging and updating the status.
I am glad it works for you.

Regards
Leo


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