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Contributor
Contributor
301 Views
Registered: ‎12-12-2018

MIPI RX Subsystem address range

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We find that the MIPI RX Subsystem is taking alot of the address space takes on the order of 0x1_0000 bytes.

This seems like alot consider the fact that the 3 components that make up the core each only take about 0x100 bytes.

is there a way to change the internal crossbar to have an address width of 0x1000 instead of 0x1_0000? (4kB instead of 64kB).

We can make an external I2C interface, but we cannot have both control of the RX controller (Hidden IP), and the D-PHY address space without using the internal crossbar.

Using a whole 128kB of address space is really wasteful when 8kB would more than suffice and not be too far in the "over optimization" realm.

 

Is this reasonable to expect in a near-term release?

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Xilinx Employee
Xilinx Employee
142 Views
Registered: ‎03-30-2016

Re: MIPI RX Subsystem address range

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Hello @markramona 

@florentwand I are having discussion with IP developer team on this matter.
If we can set a target milestone on this request, we will share on this thread.

Thanks & regards
Leo

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Xilinx Employee
Xilinx Employee
260 Views
Registered: ‎03-30-2016

Re: MIPI RX Subsystem address range

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Hello Mark @markramona 

Thank you for your feedback. I understand your concern.
Unfortunately, This is not a bug and we do not have any milestone to update MIPI CSI-2 RX Subsystem register space.

If this un-optimized address space of MIPI CSI-2 IP halted down your project,
Please escalate this feature-enhacement request via your FAE.

Thanks
Leo

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Contributor
Contributor
238 Views
Registered: ‎12-12-2018

Re: MIPI RX Subsystem address range

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There is no immediate need to have a more optimized space, it just seems like the MIPI subsystem is something you are actively working on and this is one of the (very small) pain points with have with it.

I know it requires coordination between writing the driver and the hardware, so it isn't exactly easy.

Thanks for taking the time to respond.

Moderator
Moderator
201 Views
Registered: ‎11-09-2015

Re: MIPI RX Subsystem address range

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Hi @markramona 

I do not think this is possible in near term.

The MIPI CSI2 RX IP is a subsystem, this means that it is consitued by multiple IP. As each IP need to have at least 4KB address space (minimum for an AXI4), the wrapper needs to be higher. This way the sub-IPs can still be addressed individually.

Regards


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Contributor
Contributor
189 Views
Registered: ‎12-12-2018

Re: MIPI RX Subsystem address range

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@florentw 

 

> As each IP need to have at least 4KB address space (minimum for an AXI4)

 

I'm asking only that each of the sub IPs take 4kB. Currently, each one is taking 64kB, a huge increase in the required address space.

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Xilinx Employee
Xilinx Employee
143 Views
Registered: ‎03-30-2016

Re: MIPI RX Subsystem address range

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Hello @markramona 

@florentwand I are having discussion with IP developer team on this matter.
If we can set a target milestone on this request, we will share on this thread.

Thanks & regards
Leo

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Contributor
Contributor
125 Views
Registered: ‎12-12-2018

Re: MIPI RX Subsystem address range

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Thanks @karnanl @florentw

I think this would be pretty cool to have. Again, pretty minor, but nice to have.
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Moderator
Moderator
72 Views
Registered: ‎11-21-2018

Re: MIPI RX Subsystem address range

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Hi @markramona 

 

If your question is answered or your issue is solved, please kindly mark the response which helped as solution (click on "Accept as solution" button below the reply)

 

If this is not solved/answered, please reply in the topic giving more information on your current status.

 

Thanks and Regards,

Aoife
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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