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Adventurer
Adventurer
225 Views
Registered: ‎05-27-2008

MIPI TX Subsystem minimum blanking period

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Hi,

I'm designing with the MIPI TX Subsystem core (Artix 7 baseboard) and I was wondering :

- Is there a minimum line blanking period?

- Is there a minimum frame blanking period?

Regards,

Benoit

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Xilinx Employee
Xilinx Employee
136 Views
Registered: ‎03-30-2016

Re: MIPI TX Subsystem minimum blanking period

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Hello Benoit @deltaxlx 

I am assuming that you are using MIPI CSI-2 TX Subsystem.

>- Is there a minimum line blanking period?
>- Is there a minimum frame blanking period?

MIPI CSI-2 spesification does not clarify any limitation/restriction on these blanking period min value.

but there are two things to be considered :
1. MIPI D-PHY has to changes mode from (HS mode)->(LP mode)->(HS mode), this HS/LP/HS down time can be considered as min line blanking period.
   ( See also MIPI D-PHY spec for details spec value )
DPHY_HS_LP_HS.png

    So, If you need to maximize bandwith utilization. You can try to:
    (a) Using continuous clock mode. Since this mode will reduce HS-LP-HS transition timing needed for clock lane.
    (b) Using higher line-rate setting.

2. I saw some MIPI receiver / MIPI deserializer devices that requires a spesific timing requirement
( for ex. Min blanking period, Frame start to packet header blanking time etc ), these timing requirement are beyond MIPI D-PHY spec scope.
Xilinx MIPI D-PHY RX IPs do not require additional timing requirement, but you may want to check if your MIPI receiver device requires a spesific timing.


Thanks & regards
Leo

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Xilinx Employee
Xilinx Employee
137 Views
Registered: ‎03-30-2016

Re: MIPI TX Subsystem minimum blanking period

Jump to solution

Hello Benoit @deltaxlx 

I am assuming that you are using MIPI CSI-2 TX Subsystem.

>- Is there a minimum line blanking period?
>- Is there a minimum frame blanking period?

MIPI CSI-2 spesification does not clarify any limitation/restriction on these blanking period min value.

but there are two things to be considered :
1. MIPI D-PHY has to changes mode from (HS mode)->(LP mode)->(HS mode), this HS/LP/HS down time can be considered as min line blanking period.
   ( See also MIPI D-PHY spec for details spec value )
DPHY_HS_LP_HS.png

    So, If you need to maximize bandwith utilization. You can try to:
    (a) Using continuous clock mode. Since this mode will reduce HS-LP-HS transition timing needed for clock lane.
    (b) Using higher line-rate setting.

2. I saw some MIPI receiver / MIPI deserializer devices that requires a spesific timing requirement
( for ex. Min blanking period, Frame start to packet header blanking time etc ), these timing requirement are beyond MIPI D-PHY spec scope.
Xilinx MIPI D-PHY RX IPs do not require additional timing requirement, but you may want to check if your MIPI receiver device requires a spesific timing.


Thanks & regards
Leo

View solution in original post

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Adventurer
Adventurer
111 Views
Registered: ‎05-27-2008

Re: MIPI TX Subsystem minimum blanking period

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Hi Leo,

Thanks a lot, it is now clear !

Benoit