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Adventurer
Adventurer
898 Views
Registered: ‎02-24-2009

MIPI pass trough design

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We have a MIPI connection between some chip and a displays (picture A). Now we want to do some processing on the MIPI stream using Xilinx FPGA (picture B).

 

So in the FPGA we will have a set of MIPI D_PHYs for inputing from the chip and a set of D_PHYs for output to the display. Before we are going to implement any MIPI processing we would like to make a MIPI pass through (picture C). So essentialle creating the same situation as picture A. We want to use the PG202 MIPI D-PHY core for the MIPI IO.

 

 

 

The question: can we connect the D_PHY outputs and inputs of the PG202 core back to back to creat such a pass through ?

Kees van Egmond
FAE 4 Xilinx @ Avnet Silica Netherlands
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Moderator
Moderator
1,088 Views
Registered: ‎11-09-2015

Re: MIPI pass trough design

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Hi @kvanegmond,

 

Yes, I do not see any reasons why it wouldn't works. The PG202 does not specify a specific mapping.

 

You might want to try first in simulation (use the example design and add a TX after the RX)

 

Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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2 Replies
Moderator
Moderator
1,089 Views
Registered: ‎11-09-2015

Re: MIPI pass trough design

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Hi @kvanegmond,

 

Yes, I do not see any reasons why it wouldn't works. The PG202 does not specify a specific mapping.

 

You might want to try first in simulation (use the example design and add a TX after the RX)

 

Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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Observer jura_xylon
Observer
790 Views
Registered: ‎09-30-2009

Re: MIPI pass trough design

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Not sure how this would work without some kind of an IP (csi_ctrl or dsi_ctrl) between the DPHY_RX and DPHY_TX because the tx_ppi and rx_ppi interfaces can not be connected together.

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