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Scholar trenz-al
Scholar
11,871 Views
Registered: ‎11-09-2013

MPSoC DisplayPort: no picture on ZCU102 ?

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I got as far that I see:

 

/sys/devices/platform/amba/amba:xilinx_drm/graphics/fb0# cat modes
U:1920x1200p-0

 

When monitor cable is plugged in, and error message with no cable, but monitor remains black :(

 

It is very hard to figure out what is the correct way of getting DisplayPort running ZCU102 TRD is very clear, there is also no note that DisplayPort would not work, but then in Xilinx Release notes it says:

 

DisplayPort no picture on display - FIX expected in Vivado 2016.3

 

It seems that video mode is not set?

 

 fbset

mode "1920x1200-0"
        # D: 0.000 MHz, H: 0.000 kHz, V: 0.000 Hz
        geometry 1920 1200 1920 1200 32
        timings 0 0 0 0 0 0 0
        accel true
        rgba 8/16,8/8,8/0,8/24
endmode

 

is that correct? how to enable display? I am not using the QT things from TRD, I just want something to be displayed

 

 

 

 

So what is the deal. does DP work on MPSoC/ZCU102 or do we have to wait til 2016.3 ?

 

 

 

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Scholar trenz-al
Scholar
19,018 Views
Registered: ‎11-09-2013

Re: MPSoC DisplayPort: no picture on ZCU102 ?

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I got the NEW monitor, the log was from the connection to monitor from the ZCU102 supported monitor list. DisplayPort must work with this monitor based on Xilinx supported monitor list.

 

I did think that I got the right monitor, I  did give U2414H to the purchasing department, but what I got is P2414Hb !

 

P2414H is very very similar to U241H but well it is not the same as the on Xilinx list. But I do not think buying one more monitor would make a difference. P2414H has 1920 x 1080 x 60 as native resolution so I assume it should work.

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Scholar watari
Scholar
11,860 Views
Registered: ‎06-16-2013

Re: MPSoC DisplayPort: no picture on ZCU102 ?

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Hi trenz-al

 

I don't have any suggestion to resolve your problem.

But I can explain assumed route causes to you.

 

I think that the assumed route causes are as below.

 

1) Link training error on DisplayPort between FPGA and Monitor

2) Fail to recognize video timing via EDID

3) Mismatch between embedded clock on Display Port IP  and generated clock on Monitor

4) Known/Unknown issue of Monitor

5) Known/Unknown issue of Display Port IP

 

If you can measure some signals by high end oscilloscope, you can check 1) and 3).

=> Signal Integrity or Clock frequency error or Clock jitter error (But you can not measure it)

 

If you can confirm recognized EDID value on Linux, you can check 2).

=> Software issue

 

If you can change monitor, you can check 4).

=> Compatibility issue (Xilinx needs to do plug-test to resolve this issue)

 

 

I hope this would be some of help.

 

Thank you.

Best regards,

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Scholar trenz-al
Scholar
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Registered: ‎11-09-2013

Re: MPSoC DisplayPort: no picture on ZCU102 ?

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There is no IP Core, I am using the DisplayPort block in Zynq MPSoC, we are using ES1 samples, but there is no errata that DisplayPort does not work.

 

Some weird things, with petalinux 2016.1 - initially I did see the hotplug events, but then after updating the xilinx linux kernel to support DP phy drivers, I no longer see hotplug events.

 

But there is some monitor detection working, but only once at power up.

 

Clocking, this is very weird - all the Clock to the DP (Execpt serdes PLL clock) are generated by the PS DP Block, but the DP devicetree requires some user clock, there is fix in Xilinx for QEMU to use "fake clock" I used fake si570 clock, this clock is connected to NOTHING output goes void devnul, but without this clock the system will not load drivers.

 

        xilinx_drm: xilinx_drm {
            compatible = "xlnx,drm";
            status = "disabled";
            xlnx,encoder-slave = <&xlnx_dp>;
            xlnx,connector-type = "DisplayPort";
            xlnx,dp-sub = <&xlnx_dp_sub>;
            planes {
                xlnx,pixel-format = "rgb565";
                plane0 {
                    dmas = <&xlnx_dpdma 3>;
                    dma-names = "dma0";
                };
                plane1 {
                    dmas = <&xlnx_dpdma 0>;
                    dma-names = "dma0";
                };
            };
        };

 

documentation says that dma names should be with number appended, in TRD they are without, if I use

 

                    dma-names = "dma";

 

I get kernel crash

 

                    dma-names = "dma0";

 

does not crash, but no picture either

 

https://github.com/Xilinx/device-tree-xlnx/blob/master/device_tree/data/kernel_dtsi/2016.2/zynqmp/zynqmp.dtsi

 

with this dtsi, it is 100% crash!

 

 

 

 

 

 

I think there is some driver devicetree issue, but I can not figure out what it is, no info what I can gather from the ZCU 102 TRD helps, everythign seems to be same as the TRD says (Execpt I want DP only withot the HDMI input FMC)

 

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Scholar watari
Scholar
11,836 Views
Registered: ‎06-16-2013

Re: MPSoC DisplayPort: no picture on ZCU102 ?

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Hi trenz-al

 

I have a question about the content of dts.

Why do you set pixel-format as "rbg565" at dts file ?

 

It's a little weird to connect external monitor.

 

Could you change pixel-format as "rgb888" and update related parameters (*1), too ?

 

*1)

clock frequency, bus width on axi4-stream and so on.

 

[note]

1)

DisplayPort function is consist of DisplayPort PHY (like PCI Express PHY), recovery clock/embedded clock logic and some F/W.

Also DisplayPort function (IP, Fabric, LCD monitor with DisplayPort) must be passed compliance test. 

 

2)

LCD monitor supports 8bit/10bit RGB color depth on Display Port. 

 

 

 

Thank you.

Best regards,

Scholar trenz-al
Scholar
11,829 Views
Registered: ‎11-09-2013

Re: MPSoC DisplayPort: no picture on ZCU102 ?

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I did include snippet from dtsi file, the pixel-format is set

 

&xilinx_drm {
    status = "okay";
    clocks = <&si570_2>;
    planes {
        xlnx,pixel-format = "abgr8888";
    };
};

 

there you also see the "fake" si570 as clock source, if I remove it, then drm drivers will not load..

 

all the phy init and stuff should be taken care by the drivers. There is no  IP (except the hard block in MPSOC), FPGA fabric is not used at all.

 

I think that Xilix drivers are BLEEDING, at this time, if you take xilinx dtsi and xilinx last github drivers, then it is kernel crash, so at least dtsi has to be changed (dma to dma0 to allow driver to see it)

 

I think some of the "plane" or dma stuff is not correct, but there is no known working example. ZCU102 TRD can not work as much as I can see, not with the info currently available.

 

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Registered: ‎11-09-2013

Re: MPSoC DisplayPort: no picture on ZCU102 ?

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getting slowly...

 

[    4.414440] xilinx-psgtr fd400000.zynqmp_phy: Lane:3 type:8 protocol:4 pll_locked:yes
[    4.422393] xilinx-drm-dp fd4a0000.dp: device found, version 4.010
[    4.428496] xilinx-drm-dp fd4a0000.dp: Display Port, version 1.0200 (tx)
[    4.472469] [drm:xilinx_drm_crtc_mode_set] *ERROR* failed to set a pixel clock

 

this comes when I remove the "fake" si570 clock from the drm node, with the si70 fake clock, there comes no error, but display remains black...

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Registered: ‎06-16-2013

Re: MPSoC DisplayPort: no picture on ZCU102 ?

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Hi trenz-al

 

Could you tell me "si570" and "si70" ?

 

[    4.472469] [drm:xilinx_drm_crtc_mode_set] *ERROR* failed to set a pixel clock

 

BTW, do you set a pixel clock as 148.5MHz ?

The clock frequency of FHD@60Hz (1920x1080@60Hz) is 148.5[MHz].

 

I'd like to confirm it.

 

Thank you.

Best regards,

 

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Registered: ‎11-09-2013

Re: MPSoC DisplayPort: no picture on ZCU102 ?

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            si570_2: clock-generator3@5d { /* USER MGT SI570 - u56 */
                #clock-cells = <0>;
                compatible = "silabs,si570";
                reg = <0x5d>;
                temperature-stability = <50>; /* copy from zc702 */
                factory-fout = <156250000>;
                clock-frequency = <148500000>;

 

this is from ZCU102 devicetree, but this clock is not used... the output is not connected..

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Registered: ‎06-16-2013

Re: MPSoC DisplayPort: no picture on ZCU102 ?

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Hi trenz-al

 

Could you tell me what LCD monitor do you use ?

I'd like to confirm it.

 

Thank you.

Best regards,

 

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Scholar
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Registered: ‎11-09-2013

Re: MPSoC DisplayPort: no picture on ZCU102 ?

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DELL U2142M

 

https://www.amazon.de/Dell-LED-Monitor-Reaktionszeit-h%C3%B6henverstellbar-schwarz/dp/B005JN9310

 

we got this error:

 

[    4.137760] [drm] No driver support for vblank timestamp query.
[    4.205191] xilinx-dpdma fd4c0000.dma: error intr: isr = 0x00200000, eisr = 0x00000000
[    4.221696] Console: switching to colour frame buffer device 240x75

 

seems some kind of DESC error whatever it means bit 21

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Registered: ‎11-09-2013

Re: MPSoC DisplayPort: no picture on ZCU102 ?

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the clocking is confusing, to my understanding the PS DP can work without PL being programmed, those generating al clocks internally , but then there is note that live video is not used but live video CLOCK input is used to generate timings, well we supply this clock from si570, but it doesnt seemt to solve the problems

 

 

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Xilinx Employee
Xilinx Employee
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Registered: ‎08-01-2008

Re: MPSoC DisplayPort: no picture on ZCU102 ?

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check this post
https://forums.xilinx.com/t5/Xilinx-Boards-and-Kits/ZCU102-PS-GT-problem/td-p/711089
Thanks and Regards
Balkrishan
--------------------------------------------------------------------------------------------
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Registered: ‎11-09-2013

Re: MPSoC DisplayPort: no picture on ZCU102 ?

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to @balkris This was my own post related to issue long solved.

 

=== status

 

It seems that the Xilinx drivers can not get or set the clocks (pixel clock, vert/horiz and frame rate) as they are displayed as 0, but there are no errors in the log.DP_AUX.png

Here you can see the MPSoC to query the DP model make, and getting correct response U2412M is our monitor

dp_sync.png

Here you can see the DP subsystem to push back video sync signals into PL, the line length is 1195 pixels, well monitor has 1200 in the max resolution

 

but.. the video clock settings are set to 0 Hz all, maybe the DRM does not automatically set any resolution? Still weird - only one supported resolution is reported, 1920 x 1200 x 0 HZ

 

 

 

 

 

 

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Scholar
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Registered: ‎06-16-2013

Re: MPSoC DisplayPort: no picture on ZCU102 ?

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Hi trenz-al

 

I have a question about what you want to do.

 

Why do you output FHD signal to Dell U2412M ?

 

The resolution of Dell U2412M is 1920 x 1200 (Wide UXGA). It's not FHD.

I'm not sure whether U2412M can support FHD to keep aspect ratio or not.

If U2412M support FHD to keep acpect ratio, your setting is no problem.

But I don't think so.

So, I recommend to change clock frequency or LCD monitor.

 

If you want to use Dell U2412M, could you change clock frequency from 148.5MHz, which is for FHD@60Hz,  to native dot clock (193.25MHz) or reduced blanking timing clock (154MHz) ?

The reduced blanking timing is suitable for LCD monitor.

I guess that the result will be changed.

 

Let me know if you have any question about video timing.

I will reply it as far as I know.

 

[FYI]

"VESA COORDINATED VIDEO TIMING GENERATOR" (*1)

http://www.vesa.org/vesa-standards/free-standards/

https://en.wikipedia.org/wiki/Coordinated_Video_Timings

 

*1)

User can calculate recommended video timing via CVT spreadsheet by itself. 

You can download it from www.vesa.org.

 

Thank you.

Best regards,

 

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Registered: ‎11-09-2013

Re: MPSoC DisplayPort: no picture on ZCU102 ?

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What I want is simple: do see a picture on Zynq UltraScale+ MPSoC DiplayPort, thats it.

 

I am using ZCU102 TRD design, that is supposed to work as much as I can read, but then there is petalinux known issues AR that says that ZCU102 displayport DOES NOT WORK and is supposed to be fixed in petalinux release 2016.3

 

So I am not sure what document is correct, in the ZCU102 documents there are screenshots that shows a picture coming from displayport, so I assume hardware wise it works, but driver wise? not sure.

 

the monitor we use can do 1920 x 1080 x 60hz, at least we can set this resolution if connected to PC using dell setup utility. So I think the monitor we use can do the required resolution.

 

Clock: this is the most weird thing - I have no idea where the clock is taken or used, or set, this is also not explained anywhere, the TRD does not use live video, it does however enable live video PL Ports and feeds si570 deriver pixel clock into the live video streaming port, while not delivering any live video.

 

I am using the ZCU102 settings, also delivering that clock to the live video clock input.

 

But not matter what, the bootlog DETECTS the monitor, and the resolution, but always says all clocks and timings are 0Hz, but it does not spit out any errors saying that incompatible timing or something like that.

 

fbset

mode "1920x1200-0"
        # D: 0.000 MHz, H: 0.000 kHz, V: 0.000 Hz
        geometry 1920 1200 1920 2400 32
        timings 0 0 0 0 0 0 0
        accel true
        rgba 8/16,8/8,8/0,8/24
endmode

 

this resolution is read from the monitor, it is correct max resolution, but frame rate is set to 0Hz :(

 

 

 

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Registered: ‎11-09-2013

Re: MPSoC DisplayPort: no picture on ZCU102 ?

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update: after decong the full log of the DP AUX messages I see that MSPoC has succesfully completed training on both lanes at 2.7Gbps, then set mode to normal and entered power state D0, but the DP Monitor shows no picture..
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Registered: ‎06-16-2013

Re: MPSoC DisplayPort: no picture on ZCU102 ?

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Hi trenz-al

 

Sorry for the confusion.
I mention to you again.

 

Firstly, I mention to you about "Display Port negotiation flow".
I'm probably sure that here is basic Display Port negotiation flow.
I use [n-m-X] format in this explanation.
"n" and "m" mean number of flow and "X" means source or destination equipment. ("a" means Host (MPSoC) and "b" means LCD Monitor.)


<DisplayPort negotiation flow>
[1-a/b] Link training to Display Port (like PCI Express/Physical) between Host and Monitor
[2-1-a] Request EDID via AUX (I2C) 
[2-2-b] Send EDID via AUX (I2C)
[3-a ] Recognize max. resolution and acceptable resolution
[4-1-a] Set some parameters to output actual resolution by driver (and/or internal F/W of DiplayPort IP). (physical resolution/output resolution)
ex)
  case a)
    Dell U2412M
        physical resolution 1920x1200@154[MHz] (Reduced blanking timing)
        output resolution 1920x1080 (center alliened)
  case b)
    Dell U2412M
        physical resolution 1920x1200@154[MHz] (Reduced blanking timing)
        output resolution 1920x1200
[4-2-a] Send(output) video data via DisplayPort (Embeded clock (*1))
[4-3-b] Receive(input) video data via DisplayPort (Recoveried clock (*1))


In this case, I suspect that current Xilinx DP driver doesn't support case a) at [4-1-a].
Because you encountered same situation and Xilinx announced that it will fix by Vivado 2016.3.

And as you mentioned before, I found some evidences on your posted log file. (Resolution is OK. But dot clock is not correct.)

 

I think that Xilinx driver only calculate video timing and dot clock with output resolution. Not physical resolution.

Xilinx driver doesn't consider that physical resolution and output resolution are different. I guess it's lack of consideration.

In this case, Xilinx driver should calculate video timing and dot clock with physical resolution and output resolution.

 

If you want to clear your problem before Xilinx release next Vivado, I recommend to change output resolution from 1920x1080 to 1920x1200. (case b)).
I'm not sure. But I'm probably sure that Xilinx driver can calculate correctly and you resolve this issue.

 

[note]
I already knew MPSoC has DisplayPort function. But I use "DisplayPort IP" in this explanation.

 

[notice]

*1)

Embedded clock (like dot clock) and recovered clock should be same or very close.

If not, LCD monitor confuses and DisplayPort function malfunctions, even if link training is successful.

 

Thank you.
Best regards,

 

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Registered: ‎11-09-2013

Re: MPSoC DisplayPort: no picture on ZCU102 ?

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Hi

 

thank you very much for this detailed response - I did write DP AUX to AXI stream converter and using right now hand decoded excel table to see what happens - on the DP commands all seems to be correct that is the training is passed, and power state is set to D0 (normal). I have not decoded the I2C traffic yet.

 

You say repeatedly "set resolution to 1920 x 1080" - HOW??? There is no documented way to influence the display format for the Xilinx drivers. There possible is some way in the DRM flow, but the problem is:

 

in "modes" only one display mode is listed:

 

U:1920x1200-0

 

so there are no other modes I could even try to set using the DRM drivers

 

Weird is also that when all drivers load without errors, then the HPD function does not longer work, if I disable the "fake si570" driver, then the HPD will "kind of work".

 

case a: si570 is NOT set as clock for drm

 

cable insertion causes "can not set clock, no CRTC blah errror" each time cable is plugged

 

case b: si570 is set as clock for drm

 

if cable was plugged at startup, 1920x1200-0 is recognized as only mode supported by the monitor?

if cable was NOT plugged at startup - error no supported bla from connector comes, but at cable plug event nothing happens..

 

We have already purchased a monitor from the list of supported monitors, so I am waiting for this monitor to arrive.

 

It realy seems like some driver issue but I am still afraid the drivers-devicetree is still more wrong than just the resolution (because of the HPD lacking events).

 

the answer record does not say that there is no picture on some displays, the Xilinx Answer record says there is NO output on displayport on ZCU102 at, that is function totally failing, again maybe the AR wording is misleading.

 

If the monitor does not arrive before the weekend I will start decoding the i2c traffic on DP AUX

 

 

 

 

 

 

 

 

 

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Registered: ‎11-09-2013

Re: MPSoC DisplayPort: no picture on ZCU102 ?

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UPDATE, we have know a monitor for the "SUPPORTED MONITOR" list

 

fbset

mode "1920x1080-0"
        # D: 0.000 MHz, H: 0.000 kHz, V: 0.000 Hz
        geometry 1920 1080 1920 2160 32
        timings 0 0 0 0 0 0 0
        accel true
        rgba 8/16,8/8,8/0,8/24
endmode

 

ZCU TRD does not have

 

/etc/fb.modes

 

file and I have no idea if that file is needed or not, assumed it is not needed.

 

 

 

 

fbset now detect correct resolution for this monitor, but screen is still blank, and all timings are set to 0Hz

 

So how to solve this issue?

 

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Registered: ‎11-09-2013

Re: MPSoC DisplayPort: no picture on ZCU102 ?

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 dmesg | grep drm

 

very strange, the frame rate is somwehere detected as 60Hz, but a the end fbset still says 0Hz :(


[    4.843723] [drm] Initialized drm 1.1.0 20060810
[    4.848346] [drm:drm_platform_init]
[    4.848350] [drm:drm_get_platform_dev]
[    4.848404] [drm:drm_minor_register]
[    4.848494] [drm:drm_minor_register] new minor registered 64
[    4.848498] [drm:drm_minor_register]
[    4.848501] [drm:drm_minor_register]
[    4.848571] [drm:drm_minor_register] new minor registered 0
[    4.848622] [drm:xilinx_drm_plane_probe_manager] failed to get a dp_sub
[    4.848626] [drm:xilinx_drm_load] failed to create xilinx crtc
[    4.848639] [drm] load() is defered & will be called again
[    4.854422] xilinx-drm-dp-sub fd4aa000.dp_sub: Xilinx DisplayPort Subsystem is probed
[    5.904025] [drm:drm_platform_init]
[    5.904030] [drm:drm_get_platform_dev]
[    5.904092] [drm:drm_minor_register]
[    5.904187] [drm:drm_minor_register] new minor registered 64
[    5.904191] [drm:drm_minor_register]
[    5.904195] [drm:drm_minor_register]
[    5.904265] [drm:drm_minor_register] new minor registered 0
[    5.904338] [drm:xilinx_drm_plane_create] plane->id: 0
[    5.904365] [drm:xilinx_drm_plane_create] plane->id: 1
[    5.904455] [drm:xilinx_drm_encoder_create] failed to get device driver
[    5.904459] [drm:xilinx_drm_load] failed to create xilinx encoder
[    5.904464] [drm:xilinx_drm_encoder_dpms] dpms: 3 -> 3
[    5.904482] [drm:xilinx_drm_plane_dpms] plane->id: 0
[    5.904486] [drm:xilinx_drm_plane_dpms] dpms: 3 -> 3
[    5.904496] [drm:xilinx_drm_plane_dpms] plane->id: 1
[    5.904500] [drm:xilinx_drm_plane_dpms] dpms: 3 -> 3
[    5.904508] [drm:xilinx_drm_crtc_dpms] dpms: 3 -> 3
[    5.904515] [drm] load() is defered & will be called again
[    5.918414] xilinx-drm-dp fd4a0000.dp: device found, version 4.010
[    5.924522] xilinx-drm-dp fd4a0000.dp: Display Port, version 1.0200 (tx)
[    5.959450] [drm:drm_platform_init]
[    5.959454] [drm:drm_get_platform_dev]
[    5.959511] [drm:drm_minor_register]
[    5.959595] [drm:drm_minor_register] new minor registered 64
[    5.959599] [drm:drm_minor_register]
[    5.959602] [drm:drm_minor_register]
[    5.959671] [drm:drm_minor_register] new minor registered 0
[    5.959718] [drm:xilinx_drm_plane_create] plane->id: 0
[    5.959739] [drm:xilinx_drm_plane_create] plane->id: 1
[    5.959878] [drm:drm_sysfs_connector_add] adding "DP-1" to sysfs
[    5.959883] [drm:drm_sysfs_hotplug_event] generating hotplug event
[    5.959910] [drm] Supports vblank timestamp caching Rev 2 (21.10.2013).
[    5.966445] [drm] No driver support for vblank timestamp query.
[    5.972350] [drm:xilinx_drm_encoder_dpms] dpms: 3 -> 3
[    5.972355] [drm:xilinx_drm_crtc_dpms] dpms: 3 -> 3
[    5.972362] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:24:DP-1]
[    5.973411] [drm:xilinx_drm_connector_detect] status: 1
[    5.973418] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:24:DP-1] status updated from unknown to connected
[    5.992293] [drm:drm_add_display_info] DP-1: Assigning EDID-1.4 digital sink color depth as 8 bpc.
[    5.992307] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:24:DP-1] probed modes :
[    5.992317] [drm:drm_mode_debug_printmodeline] Modeline 26:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
[    5.992325] [drm:drm_mode_debug_printmodeline] Modeline 29:"1600x900" 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5
[    5.992333] [drm:drm_mode_debug_printmodeline] Modeline 34:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
[    5.992340] [drm:drm_mode_debug_printmodeline] Modeline 28:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
[    5.992348] [drm:drm_mode_debug_printmodeline] Modeline 27:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
[    5.992356] [drm:drm_mode_debug_printmodeline] Modeline 35:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
[    5.992364] [drm:drm_mode_debug_printmodeline] Modeline 36:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
[    5.992372] [drm:drm_mode_debug_printmodeline] Modeline 37:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
[    5.992379] [drm:drm_mode_debug_printmodeline] Modeline 30:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
[    5.992387] [drm:drm_mode_debug_printmodeline] Modeline 31:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
[    5.992395] [drm:drm_mode_debug_printmodeline] Modeline 32:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
[    5.992402] [drm:drm_mode_debug_printmodeline] Modeline 33:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
[    5.992406] [drm:drm_setup_crtcs]
[    5.992412] [drm:drm_enable_connectors] connector 24 enabled? yes
[    5.992418] [drm:drm_target_preferred] looking for cmdline mode on connector 24
[    5.992423] [drm:drm_target_preferred] looking for preferred mode on connector 24 0
[    5.992427] [drm:drm_target_preferred] found mode 1920x1080
[    5.992431] [drm:drm_setup_crtcs] picking CRTCs for 0x0 config
[    5.992437] [drm:drm_setup_crtcs] desired mode 1920x1080 set on crtc 22 (0,0)
[    5.992445] [drm:xilinx_drm_fbdev_create] surface width(1920), height(1080) and bpp(32)
[    5.996754] [drm:drm_crtc_helper_set_config]
[    5.996759] [drm:drm_crtc_helper_set_config] [CRTC:22:crtc-0] [FB:39] #connectors=1 (x y) (0 0)
[    5.996763] [drm:drm_crtc_helper_set_config] crtc has no fb, full mode set
[    5.996765] [drm:drm_crtc_helper_set_config] modes are different, full mode set
[    5.996770] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
[    5.996776] [drm:drm_mode_debug_printmodeline] Modeline 38:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
[    5.996778] [drm:drm_crtc_helper_set_config] connector dpms not on, full mode switch
[    5.996779] [drm:drm_crtc_helper_set_config] encoder changed, full mode switch
[    5.996781] [drm:drm_crtc_helper_set_config] crtc changed, full mode switch
[    5.996784] [drm:drm_crtc_helper_set_config] [CONNECTOR:24:DP-1] to [CRTC:22:crtc-0]
[    5.996787] [drm:drm_crtc_helper_set_config] attempting to set mode from userspace
[    5.996792] [drm:drm_mode_debug_printmodeline] Modeline 38:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
[    5.996798] [drm:drm_crtc_helper_set_mode] [CRTC:22:crtc-0]
[    5.996800] [drm:xilinx_drm_encoder_dpms] dpms: 3 -> 3
[    5.996803] [drm:xilinx_drm_crtc_dpms] dpms: 3 -> 3
[    5.997850] [drm:xilinx_drm_plane_mode_set] plane->id: 0
[    5.997854] [drm:xilinx_drm_plane_mode_set] h: 1920(0), v: 1080(0)
[    5.997856] [drm:xilinx_drm_plane_mode_set] bpp: 4
[    5.997862] [drm:drm_crtc_helper_set_mode] [ENCODER:23:TMDS-23] set [MODE:38:1920x1080]
[    5.997864] [drm:xilinx_drm_encoder_mode_set] h: 1920, v: 1080
[    5.997866] [drm:xilinx_drm_encoder_mode_set] refresh: 60, pclock: 148500 khz
[    6.012870] [drm:xilinx_drm_crtc_dpms] dpms: 3 -> 0
[    6.012877] [drm:xilinx_drm_plane_dpms] plane->id: 0
[    6.012879] [drm:xilinx_drm_plane_dpms] dpms: 3 -> 0
[    6.012884] [drm:xilinx_drm_plane_commit] plane->id: 0
[    6.012895] [drm:xilinx_drm_encoder_dpms] dpms: 3 -> 0
[    6.014008] [drm:drm_calc_timestamping_constants] crtc 22: hwmode: htotal 2200, vtotal 1125, vdisplay 1080
[    6.014012] [drm:drm_calc_timestamping_constants] crtc 22: clock 148500 kHz framedur 16666666 linedur 14814
[    6.014015] [drm:drm_crtc_helper_set_config] Setting connector DPMS state to on
[    6.014017] [drm:drm_crtc_helper_set_config]         [CONNECTOR:24:DP-1] set DPMS on
[    6.014020] [drm:xilinx_drm_crtc_dpms] dpms: 0 -> 0
[    6.014022] [drm:xilinx_drm_encoder_dpms] dpms: 0 -> 0
[    6.014026] [drm:drm_framebuffer_reference] ffffffc070c15800: FB ID: 39 (1)
[    6.014115] [drm:drm_crtc_helper_set_config]
[    6.014118] [drm:drm_crtc_helper_set_config] [CRTC:22:crtc-0] [FB:39] #connectors=1 (x y) (0 0)
[    6.014123] [drm:drm_crtc_helper_set_config] [CONNECTOR:24:DP-1] to [CRTC:22:crtc-0]
[    6.014125] [drm:drm_framebuffer_reference] ffffffc070c15800: FB ID: 39 (2)
[    6.014128] [drm:drm_framebuffer_unreference] ffffffc070c15800: FB ID: 39 (3)
[    6.038382] [drm:drm_crtc_helper_set_config]
[    6.038386] [drm:drm_crtc_helper_set_config] [CRTC:22:crtc-0] [FB:39] #connectors=1 (x y) (0 0)
[    6.038390] [drm:drm_crtc_helper_set_config] [CONNECTOR:24:DP-1] to [CRTC:22:crtc-0]
[    6.038393] [drm:drm_framebuffer_reference] ffffffc070c15800: FB ID: 39 (2)
[    6.038395] [drm:drm_framebuffer_unreference] ffffffc070c15800: FB ID: 39 (3)
[    6.069002] xilinx-drm amba:xilinx_drm: fb0:  frame buffer device
[    6.085412] [drm] Initialized xilinx_drm 1.0.0 20130509 on minor 0
[   16.102524] [drm:xilinx_drm_connector_detect] status: 1
[   16.102532] [drm:drm_sysfs_hotplug_event] generating hotplug event
[   16.102569] [drm:drm_fb_helper_hotplug_event]
[   16.102576] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:24:DP-1]
[   16.103695] [drm:xilinx_drm_connector_detect] status: 1
[   16.122523] [drm:drm_property_unreference_blob] ffffffc071248a00: blob ID: 25 (1)
[   16.122563] [drm:drm_add_display_info] DP-1: Assigning EDID-1.4 digital sink color depth as 8 bpc.
[   16.122585] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:24:DP-1] probed modes :
[   16.122594] [drm:drm_mode_debug_printmodeline] Modeline 26:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
[   16.122603] [drm:drm_mode_debug_printmodeline] Modeline 29:"1600x900" 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5
[   16.122611] [drm:drm_mode_debug_printmodeline] Modeline 34:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
[   16.122619] [drm:drm_mode_debug_printmodeline] Modeline 28:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
[   16.122627] [drm:drm_mode_debug_printmodeline] Modeline 27:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
[   16.122635] [drm:drm_mode_debug_printmodeline] Modeline 35:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
[   16.122643] [drm:drm_mode_debug_printmodeline] Modeline 36:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
[   16.122650] [drm:drm_mode_debug_printmodeline] Modeline 37:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
[   16.122658] [drm:drm_mode_debug_printmodeline] Modeline 30:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
[   16.122666] [drm:drm_mode_debug_printmodeline] Modeline 31:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
[   16.122674] [drm:drm_mode_debug_printmodeline] Modeline 32:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
[   16.122682] [drm:drm_mode_debug_printmodeline] Modeline 33:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
[   16.122690] [drm:drm_setup_crtcs]
[   16.122695] [drm:drm_enable_connectors] connector 24 enabled? yes
[   16.122701] [drm:drm_target_preferred] looking for cmdline mode on connector 24
[   16.122705] [drm:drm_target_preferred] looking for preferred mode on connector 24 0
[   16.122710] [drm:drm_target_preferred] found mode 1920x1080
[   16.122714] [drm:drm_setup_crtcs] picking CRTCs for 4096x4096 config
[   16.122721] [drm:drm_setup_crtcs] desired mode 1920x1080 set on crtc 22 (0,0)
[   16.122731] [drm:drm_crtc_helper_set_config]
[   16.122738] [drm:drm_crtc_helper_set_config] [CRTC:22:crtc-0] [FB:39] #connectors=1 (x y) (0 0)
[   16.122749] [drm:drm_crtc_helper_set_config] [CONNECTOR:24:DP-1] to [CRTC:22:crtc-0]
[   16.122755] [drm:drm_framebuffer_reference] ffffffc070c15800: FB ID: 39 (2)
[   16.122760] [drm:drm_framebuffer_unreference] ffffffc070c15800: FB ID: 39 (3)

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Scholar watari
Scholar
9,487 Views
Registered: ‎06-16-2013

Re: MPSoC DisplayPort: no picture on ZCU102 ?

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Hi trenz-al

 

I'd like to clear what you want to do with Dell U2412M.

Here is my understanding.

Is it correct ?

 

[My understanding]

- Display 1920x1200@60Hz/32bit (RGBA) via DP on Dell U2412M

- DP IP uses 2 lanes and the rate of one lane is 2.7Gbps.

 

If yes, this result is correct. it's lack of bandwidth. 

So Xilinx driver removes native video timing of Dell U2412M from supported video timing list and DP IP set clock frequency or v frame rate as 0 at "Main Stream Attribute Data area". (*1)

 

I'd like to clear whether my explanation is correct or not.

So, could you explain your environment, too ?

 

Also, 

Can you change what you want to do from 1920x1200@60Hz/32bit (RGBA) to 1920x1200@60Hz/24bit (RGB) ?

or

Can you change other LCD Monitor ( Resolution is 1920x1080) ?

 

[note]

*1)

Of cause, If Xilinx driver support to output video signal as followings and Dell U2412M support it, it's OK.

But I'm probably sure that current Xilinx driver doesn't support it.

 

[4-1-a] Set some parameters to output actual resolution by driver (and/or internal F/W of DiplayPort IP). (physical resolution/output resolution)
ex)
  case c)
    Dell U2412M
        physical resolution 1920x1080@148.5[MHz] (Reduced blanking timing)
        output resolution 1920x1080

 

 

Thank you.

Best regards,

 

 

Scholar watari
Scholar
9,475 Views
Registered: ‎06-16-2013

Re: MPSoC DisplayPort: no picture on ZCU102 ?

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Hi trenz-al

 

> [    5.996759] [drm:drm_crtc_helper_set_config] [CRTC:22:crtc-0] [FB:39] #connectors=1 (x y) (0 0)
> [    5.996763] [drm:drm_crtc_helper_set_config] crtc has no fb, full mode set
> [    5.996765] [drm:drm_crtc_helper_set_config] modes are different, full mode set

 

I'm probably sure that I found an evidence which Xilinx driver doesn't support.

 

DRM says "modes are different, full mode set". It means that Xilinx driver want to output screen as case a).

However, because of current Xilinx driver is lack of consideration, it's occurred that vertical frequency is 0Hz.

 

If you check I2C protocol to negotiate physical resolution and acceptable resolution by EDID, you clarify route cause and how to resolve it.

 

I think that it makes sense, but it's a bug or lack of consideration issue.

 

 

Thank you.

Best regards,

 

Scholar trenz-al
Scholar
19,019 Views
Registered: ‎11-09-2013

Re: MPSoC DisplayPort: no picture on ZCU102 ?

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I got the NEW monitor, the log was from the connection to monitor from the ZCU102 supported monitor list. DisplayPort must work with this monitor based on Xilinx supported monitor list.

 

I did think that I got the right monitor, I  did give U2414H to the purchasing department, but what I got is P2414Hb !

 

P2414H is very very similar to U241H but well it is not the same as the on Xilinx list. But I do not think buying one more monitor would make a difference. P2414H has 1920 x 1080 x 60 as native resolution so I assume it should work.

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Scholar trenz-al
Scholar
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Registered: ‎11-09-2013

Re: MPSoC DisplayPort: no picture on ZCU102 ?

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* Display P2141Hb max and native resolution 1920 x 1080 x 60hz

* DZU+ Displayport uses 2 lanes 2.7Gbit

 

I am very sorry, but I really do not know how to force any of the DRM drivers to use any different parameters, I only know the parametes that are in devicetree and those all seem to be plausible. It is not possible to change the resolution frame rate or pixel clock in devicetree.

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Scholar trenz-al
Scholar
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Registered: ‎11-09-2013

Re: MPSoC DisplayPort: no picture on ZCU102 ?

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Displayport works no issues. I better save the configs now! :)

 

weird is that fbset still says 0Hz

 

mode "1920x1080-0"
        # D: 0.000 MHz, H: 0.000 kHz, V: 0.000 Hz
        geometry 1920 1080 1920 2160 32
        timings 0 0 0 0 0 0 0
        accel true
        rgba 8/16,8/8,8/0,8/24
endmode

 

but on DP Monitor there is partial boot log! and Monitor info says 1920x1080x60Hz

some timings must be bit off, the picture is shifted left some first pixels are missing but otherwise there is DP on ZU+

 

 

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Scholar watari
Scholar
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Registered: ‎06-16-2013

Re: MPSoC DisplayPort: no picture on ZCU102 ?

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Hi trenz-al

 

I'm glad to hear from you and you already solved this topics.

However I'm just interested that fbset still says 0Hz.

 

> mode "1920x1080-0"
>         # D: 0.000 MHz, H: 0.000 kHz, V: 0.000 Hz
>         geometry 1920 1080 1920 2160 32
>         timings 0 0 0 0 0 0 0
>         accel true
>         rgba 8/16,8/8,8/0,8/24
> endmode

 

How do you see it ? By log file (like messages file)  ? By generated file (Where do you see it) ?

 

Also, I'd like to ask you. Do you use X-Window system ?

If yes, I guess you resolve that the picture is shifted left some first pixels to modify Xorg.conf at video timing section by yourself.

 

[note]

As you mentioned before, I'm sure that Xilinx should modify DRM driver to enhance connectivity issue....

 

Thank you.

Best regards,

 

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Scholar trenz-al
Scholar
9,312 Views
Registered: ‎11-09-2013

Re: MPSoC DisplayPort: no picture on ZCU102 ?

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Ok, what we see

 

ther is PARTIAL bootlog on the display, not from the beginning not from the end..

picture is shifted

 

when I type

 

fbset

 

I see correct resolution, but but framerate set to 0Hz

 

framebuffer works, I can dd to the fb0 but after a while it goes into standby

 

we do not yet have X, that is peanuts nuts when the framebuffer itself is there

 

 

 

 

 

 

 

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Scholar watari
Scholar
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Registered: ‎06-16-2013

Re: MPSoC DisplayPort: no picture on ZCU102 ?

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Hi trenz-al

 

Thank you for your explanation.

 

Could you execute the following command (FHD timing/Defined by CEA-861) at your MPSoC/Linux ?

 

% fbset -t 6734 148 88 36 4 44 5 -hsync high -vsync high

 

Did it change ?

I guess you resolve shift pixel issue...

 

[note]

Here is my understanding for fbset command.

It's my memo and share my understanding.

Let me know if you find misunderstanding.

But my understanding is based on LCD monitor's experience. (similar X-window setting.)

 

% fbset -t <dot clock[ps]> <horizontal back porch[pixel]> <horizontal front porch[pixel]> <vertical back porch[line]> <vertical front porch[line]> <horizontal sync width[pixel]> <vertical sync width[line]> -hsync <hsync polarity> -vsync <vsync polarity>

 

Thank you.

Best regards,

 

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Scholar trenz-al
Scholar
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Registered: ‎11-09-2013

Re: MPSoC DisplayPort: no picture on ZCU102 ?

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we did

 

fbset -t 6734 148 88 36 4 44 5 -hsync high -vsync high
fbset: FBIOPUT_VSCREENINFO: Invalid argument

 

also valid modes include one mode with 0Hz

 

root@TEBF0808:/sys/class/graphics/fb0# cat modes
U:1920x1080p-0

 

and current mode is not set at all..

 

but display works, uh weird.

 

 

 

 

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Scholar watari
Scholar
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Registered: ‎06-16-2013

Re: MPSoC DisplayPort: no picture on ZCU102 ?

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Hi trenz-al

 

Sorry. I have a misunderstanding how to use "fbset".

Could you execute the following command ?

 

% fbset -pixclock 6734 -xres 1920 -yres 1080 -hsync high -vsync high -left 148 -right 88 -upper 36 -lower 4 -hslen 44 -vslen 5

 

Did it change ?

 

Thank you.

Best regards,

 

 

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