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Contributor
Contributor
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Registered: ‎05-09-2018

MPSoc DisplayPort Bare-metal Live Input

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Live video input does not show up on monitor connected to DisplayPort of the ZCU102 evaluation board when configuring the A/V buffer to use the PL timing.  If we hack the A/V buffer driver, forcing it to use the PS internally generated timing, the live input is displayed (just not properly sync'ed to the source obviously).  We used the Wiki (Vivado 2018.1) bare-metal DisplayPort example as our starting point and the only helpful documentation appears to be the TRM (and online register reference).  The timing looks correct according to the ILA, with all signal sync and data lines changing on the DP clock rising edge.  We're not sure what the problem may be... GT reference clock?  We'd appreciate pointers on how to debug (status register, etc).

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Moderator
Moderator
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Registered: ‎11-09-2015

Re: MPSoc DisplayPort Bare-metal Live Input

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HI @malburgj,

 

Please do not tag me when starting a topic. This does not encourage me to reply and you will not get any priority over other members of the community. In fact, this might have the opposite effect. Also, this is a community topic. Everybody can answer you not only me or a XIlinx employee. Some members are really knowledgeable, even more than Xilinx employees.

 

With that say let me try to help you now.

 

When using the live input, you need to be sure that you are using a correct timing. The timing should be correct coming from the PL as this is the one which will be use at the output. The internal timing is usually reserved for using the video from the DPDMA.

 

The recommended part of the p963 of UG1085 just means that you need to enable the live input to be able to use the timing from the PL. This might be in the case you want to use the timing from the PL while using the data from the pipe on the PS.

 

The note is for the other way. If you are using video from the PL, you should use the VPLL internally for timing or the timing from a VTC in the PL. But I would recommend to use the VTC from the PL if using the live input


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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Contributor
Contributor
1,292 Views
Registered: ‎05-09-2018

Re: MPSoc DisplayPort Bare-metal Live Input

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@florentw  Any recommendations?

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Contributor
Contributor
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Registered: ‎05-09-2018

Re: MPSoc DisplayPort Bare-metal Live Input

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@florentw  As of right now, we're able to display non-live graphics input over TPG or non-live video input no problem.  We have Xylon's logiCVC configured to spit out 1080p data (able to display on HDMI output using Avnet driver) which is connected to the dp live video input.  The graphics input data has a constant block with red as the 36-bit color.  We used the ILA to verify there's data on the DP live output so I'm guessing A/V buffer is configured properly its not an issue with the video input timing?  I'm struggling to understand what the 'use PL timing' bit is doing to the DP subsystem.  I don't understand the figure, RECOMMENDED or Note on page 963 of UG1085.  I believe our issue is with the source controller or between the source controller and A/V buffer manager, thoughts?

 

I'd like to verify the internal VTC is detecting the proper timing, but it doesn't look like I can access a register with the detected timing signals, am I missing something?

 

I don't get how the DP source controller synchronizes with the PL input timing signals?  Or does it not need to because the A/V Buffer Manager is buffering the data (i.e. the timing between A/V buffer input and DP source controller are completely independent)?

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Moderator
Moderator
1,228 Views
Registered: ‎11-09-2015

Re: MPSoc DisplayPort Bare-metal Live Input

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HI @malburgj,

 

Please do not tag me when starting a topic. This does not encourage me to reply and you will not get any priority over other members of the community. In fact, this might have the opposite effect. Also, this is a community topic. Everybody can answer you not only me or a XIlinx employee. Some members are really knowledgeable, even more than Xilinx employees.

 

With that say let me try to help you now.

 

When using the live input, you need to be sure that you are using a correct timing. The timing should be correct coming from the PL as this is the one which will be use at the output. The internal timing is usually reserved for using the video from the DPDMA.

 

The recommended part of the p963 of UG1085 just means that you need to enable the live input to be able to use the timing from the PL. This might be in the case you want to use the timing from the PL while using the data from the pipe on the PS.

 

The note is for the other way. If you are using video from the PL, you should use the VPLL internally for timing or the timing from a VTC in the PL. But I would recommend to use the VTC from the PL if using the live input


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
Contributor
Contributor
1,210 Views
Registered: ‎05-09-2018

Re: MPSoc DisplayPort Bare-metal Live Input

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@florentw Sorry I only tagged you because in another forum post (https://forums.xilinx.com/t5/Embedded-Linux/Zynq-UltraScale-Live-Video-Input-Output/m-p/782662/highlight/true#M20899) I was reading you apologized for missing the author's thread; since I'm new to this forum I didn't know if it was common for the moderates to miss threads.  I'll refrain from doing so in the future.

 

I tried using both the VTC and logiCVC (third-party IP) to generate 1080p timing and got no video with either.  If you think its an issue with the timing, I'll use the VTC detect feature to verify the timing.

 

Regarding the figure on page 963, the lines connected to the top-right MUX are confusing; the way the lines are drawn it looks like the top-right mux inputs and output are shorted (line from VPLL buffer touches both inputs to mux and appears to continue to the 'dp_live_video_in_clk' line connecting the mux output, DP controller, and video input).  Also, what controls the two mux shown in the figure? Does AV_BUFF_AUD_VID_CLK_SOURCE register control both?  Should the DP controller mux select the clock from PL when using the live input?  If yes, what register is used to do so?

 

Does the DP source controller generate its own timing, independent from the A/V Buffer (i.e. doesn't have to be synchronized to the PL live input timing because the A/V Buffer is buffering the live video data?)

 

I don't understand how the driver allows you to choose from using the VPLL or PL timing; the function XAVBuf_SetAudioVideoClkSrc() appears to 

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Contributor
Contributor
1,160 Views
Registered: ‎05-09-2018

Re: MPSoc DisplayPort Bare-metal Live Input

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@florentw Reading the registers from the VTC detector, the input timing (front porch, back porch and sync width) was off by one for both vertical and horizontal, though the hsync looked correct in the ILA? (still need to look at other timing variables).  I was able to customize the source timing and now have video coming out on displayPort as well the VTC detector video mode changed to 1080p.   Now I need to look into why I needed to customize the source timing.

 

Unless I'm missing something, I'm curious why Xilinx embedded a VTC in the DP subsystem and didn't provide registers for the  detected / generated timing variables.

 

Thanks for you help.

Moderator
Moderator
1,136 Views
Registered: ‎11-09-2015

Re: MPSoc DisplayPort Bare-metal Live Input

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HI @malburgj,

 

Thank you for sharing you findings.

The VTC is only a generator, not a detector. However, you should be able to configure the timing. When you are using the live input and the VTC from the DP controller, you need to make sure both timing are perfectly matching


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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