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Visitor quanglam
Visitor
6,942 Views
Registered: ‎11-21-2007

Make the design in AccelDSP as a component for a design in ISE

Hi all,
 

Can we use HDL files which are generated by AccelDSP as a component for other design in Xilinx ISE or simulation in Modelsim?
Is there anny way to make the design in AccelDSP as a component for a design in ISE?
 
Best regards. 
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2 Replies
Xilinx Employee
Xilinx Employee
6,913 Views
Registered: ‎08-21-2007

Re: Make the design in AccelDSP as a component for a design in ISE

Hello,
 
There isn't a fully automated way, but you can incorporate AccelDSP VHDL/Verilog just like VHDL/Verilog that you wrote.  You can instantiate the top level AccelDSP block in your larger VHDL/Verilog design within ISE.  I hope that helps.
 
Best regards,
Tim
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Visitor quanglam
Visitor
6,873 Views
Registered: ‎11-21-2007

Re: Make the design in AccelDSP as a component for a design in ISE

Thankyou Timv, I succeeded to instantiate the top level AccelDSP block in a larger VHDL design within ISE.
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