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Observer tl_rtclancy
Observer
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Registered: ‎12-13-2017

Mapping of SDI Y/C to outputs of SDI Receiver Subsystem

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The PG290 SMPTE UHD-SDI Receiver Subsystem v2.0 optionally provides an output that looks like the following:

 

SDI_DS_OUT_ds1[9:0]
SDI_DS_OUT_ds2[9:0]

SDI_DS_OUT_ds3[9:0]
SDI_DS_OUT_ds4[9:0]
SDI_DS_OUT_ds5[9:0]
SDI_DS_OUT_ds6[9:0]
SDI_DS_OUT_ds7[9:0]
SDI_DS_OUT_ds8[9:0]

 

Has anyone seen documentation on how the YCC component streams of the SDI stream map to the 8 RX SS output streams?

 

Best regards,

Bob

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Moderator
Moderator
953 Views
Registered: ‎10-04-2017

Re: Mapping of SDI Y/C to outputs of SDI Receiver Subsystem

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Hi @tl_rtclancy,

 

The UHD-SDI Receiver SubSystem has the option of converting the data into the common AXI stream format. 2018-06-26 11_19_06-Xilinx Documentation Navigator 2017.2 -  http___www.xilinx.com_support_documenta.png

 

If you choose to use the native SDI interface, please take a look at the standards for the interface. You will be looking specifically at ST 2082-x.

2018-06-26 11_21_34-Xilinx Documentation Navigator 2017.2 -  http___www.xilinx.com_support_documenta.png

Regards,

Sam

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3 Replies
Moderator
Moderator
954 Views
Registered: ‎10-04-2017

Re: Mapping of SDI Y/C to outputs of SDI Receiver Subsystem

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Hi @tl_rtclancy,

 

The UHD-SDI Receiver SubSystem has the option of converting the data into the common AXI stream format. 2018-06-26 11_19_06-Xilinx Documentation Navigator 2017.2 -  http___www.xilinx.com_support_documenta.png

 

If you choose to use the native SDI interface, please take a look at the standards for the interface. You will be looking specifically at ST 2082-x.

2018-06-26 11_21_34-Xilinx Documentation Navigator 2017.2 -  http___www.xilinx.com_support_documenta.png

Regards,

Sam

Don't forget to reply, kudo, and accept as solution.

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Observer tl_rtclancy
Observer
711 Views
Registered: ‎12-13-2017

Re: Mapping of SDI Y/C to outputs of SDI Receiver Subsystem

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I had thought the mapping of the Y/C datastreams at the output of the core would match the order in the multiplex. 

 

e.g. 

For SMPTE 425M the order is C/Y so I had expected C to be in the cores output datastream1 and Y to be in output datastream2. This turns out not to be the case. I do notice now that 425M calls the Y data stream data stream 1 and C data stream 2 which matches what the core is doing so I am all set on this one. I do think however that Xilinx could save users some time by specifying the mapping of the Y/C streams to the output of the core in the PG rather than having them wade through the various SMPTE docs or chipscoping the core to conclusively determine the mapping.

 

Thanks.

Bob

 

 

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Moderator
Moderator
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Registered: ‎10-04-2017

Re: Mapping of SDI Y/C to outputs of SDI Receiver Subsystem

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Hi Bob,

 

Thank you for the feedback.

I will take this into consideration when we update the SDI documentation.

 

Regards,

Sam

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Xilinx Video Design Hub
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