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Contributor
Contributor
272 Views
Registered: ‎05-27-2008

Modifying Video Test Pattern Generator example design

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The Video Test Pattern Generator source code (main.c) supports three video modes:  1080P, 4K30, and 4K60.

I would like to modify this code to add support for 1080P30.  Here are the changes to the code I plan on doing:

1. add a 1080P30 video mode & mode_index

2. add an additional entry in the ClkOut_Frac and ClkOut_Div constant arrays  (would these be half of the values of the 1080P60 entries?)

3. add code to set the test mode to 1080P30, call videoClockConfig with the new test mode, then call videoIpConfig with the new test mode

4. add comments accordingly.

Is there anything else that needs to be done?

Thanks!

jd
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1 Solution

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Moderator
Moderator
243 Views
Registered: ‎11-09-2015

Re: Modifying Video Test Pattern Generator example design

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HI @jdehaven and @sebo 

The example design of the test pattern generator is not outputing any video so you will not be fully able to check. As long as the VTC and TPG configuration will match, the AXI4-Stream to video out will lock.

I have shown how to support multiple resolution with a TPG design using the clock from the MMCM in my Video Series 22: Supporting multiple video resolutions on ZC702 HDMI . This is actually outputting on board. However, as this is using the ADV7511 so you can only go up to 1080p60.

Is there a specific reason why you are using the TPG example design and not any other? What will be your video interface? If you are planning to use the HDMI TX Subsystems, why not using directly the example design for the HDMI TX subsystems. It should include the test pattern generator and should demonstrate many different resoltion, including the resolution you are looking at.

There are some najor differences with the TPG example design. One is about the clocking. In the HDMI example design, we use a clock generator external to the device. The video phy driver controls this device to set the correct frequency.

If you are not willing to use another example design than the TPG, yes I think your steps looks correct on the SW side (but I didn't check in details so as @sebo , you might need to test to confirm). But you need to make sure you have done the modification in the HW as well. I.e. you will need to change the default frequency of the clocking wizard to support 4k60 (your maximum resolution to have the correct constraint) and to change the PPC configration of the TPG.

Regards


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Explorer
Explorer
259 Views
Registered: ‎03-17-2011

Re: Modifying Video Test Pattern Generator example design

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@jdehaven,

Why don't you test this and see how it goes? You can use ILA, VIO and export signals to verify the video timings.

--Sebastien
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Moderator
Moderator
244 Views
Registered: ‎11-09-2015

Re: Modifying Video Test Pattern Generator example design

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HI @jdehaven and @sebo 

The example design of the test pattern generator is not outputing any video so you will not be fully able to check. As long as the VTC and TPG configuration will match, the AXI4-Stream to video out will lock.

I have shown how to support multiple resolution with a TPG design using the clock from the MMCM in my Video Series 22: Supporting multiple video resolutions on ZC702 HDMI . This is actually outputting on board. However, as this is using the ADV7511 so you can only go up to 1080p60.

Is there a specific reason why you are using the TPG example design and not any other? What will be your video interface? If you are planning to use the HDMI TX Subsystems, why not using directly the example design for the HDMI TX subsystems. It should include the test pattern generator and should demonstrate many different resoltion, including the resolution you are looking at.

There are some najor differences with the TPG example design. One is about the clocking. In the HDMI example design, we use a clock generator external to the device. The video phy driver controls this device to set the correct frequency.

If you are not willing to use another example design than the TPG, yes I think your steps looks correct on the SW side (but I didn't check in details so as @sebo , you might need to test to confirm). But you need to make sure you have done the modification in the HW as well. I.e. you will need to change the default frequency of the clocking wizard to support 4k60 (your maximum resolution to have the correct constraint) and to change the PPC configration of the TPG.

Regards


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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Explorer
Explorer
238 Views
Registered: ‎03-17-2011

Re: Modifying Video Test Pattern Generator example design

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Hi @florentw 

Thanks for clarifying this. Yes, TPG can not be used to drive a video output. As for the tests I was suggesting, I meant measuring the framerate using the AXI Stream tuser signal which is a pulse at the begining of each first pixel of a new image frame. Moreover, using the tlast, you can count the lines and check the format. You can even count the pixel per line. that's easy to check using an ILA.

Another way, could to use another GPIO AXI PL IP to get back the line & pixel counters using software. For the framerate though, I'd create a pulse, export it on a pin and measure the frequency using a scope.

--Sebastien
Contributor
Contributor
225 Views
Registered: ‎05-27-2008

Re: Modifying Video Test Pattern Generator example design

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I should have noted that the Video TPG example design we are using has been modifed to send the video output to the ADV7511 on the KC705 board.

The design for the final product will take native video in process the video in a custom IP block, then output parallel video to a V-by-One interface device.  

The goal here is just to learn how changing between different video resolutions works on the software side of things and learn and how the video clock structure is manipulated when changing video modes.  The HDMI example designs may be an option to demonstrate details for changing video formats.

jd
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Newbie paulat
Newbie
205 Views
Registered: ‎07-19-2019

Re: Modifying Video Test Pattern Generator example design

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Hi,

Can anyone provide the register values for the following arrays that would yield clocks for 1080p30. 

Can you also provide register descriptions of each?  And the method to calculate the values in each field.

 

 

From the original question above. ...referencing the test pattern generator main.c

Const int clkout_frac[3][XVID_PPC_NUM_SUPPORTED] =

{  {250, 500, 0, 0}, //1080p60

    {125, 250, 500,0}, //4k30

    {0, 125, 250, 500} //4k60

};

const int clkout_div[3][XVID_PPC_NUM_SUPPORTED]=

{  {6, 12, 25, 50},  //1080p

    {3,  6, 12, 25}, //4k30

     {0, 3, 6, 12}  //4k60

};

Very much appreciated!!!

 

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Moderator
Moderator
165 Views
Registered: ‎11-09-2015

Re: Modifying Video Test Pattern Generator example design

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Hi @paulat 

The arrays are programming the MMCM which is driving the video clock. All the details can be found in the Clocking Wizard PG065 and as mentionned previously, this is what I am talking about in my Video Series 22: Supporting multiple video resolutions on ZC702 HDMI  so you might want to read it.

The clocking wizard clocking the video pipeline has a 100MHz input. So you can get the VCO frequency with the following formula:

VCO Frequency = (Input Clock Frequency) * (CLKFBOUT_MULT)/DIVCLK_DIVIDE

VCO Frequency = 100MHz * 37.125/4 = 928.125MHz

Then to get your output clock you can get the clkout_frac and clkout_div parameters. Assuming you want 1080p60 and you are in 1PPC, you will use the following value from the example clkout_frac = 250 abd clkout_div = 6.

So your ouput clock will be:

Clkout = VCO Frequency / (clkout_div.clkout_frac) = 928.125MHz / 6.250 = 148.5MHz

This is the pixel clock you need for 1080p60.

For 1080p30 with 1 PPC, as the required pixel clock is  you would need to devide the VCO frequency by 12.5. Then to complete the table, you just have to multiply by 2 the value between colums:

 const int ClkOut_Frac[3][XVIDC_PPC_NUM_SUPPORTED] =
{ {500, 0, 0 , 0}, //1080p30
...
const int ClkOut_Div[3][XVIDC_PPC_NUM_SUPPORTED] =
{ {12, 25, 50, 100}, //1080p30

Let me know if anything is still unclear (but please read Video Series 22: Supporting multiple video resolutions on ZC702 HDMI  first as again, all is explained)

Regards


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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Moderator
Moderator
148 Views
Registered: ‎11-09-2015

Re: Modifying Video Test Pattern Generator example design

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Hi @paulat 

Please not that I have edited my previous reply. I overlooked that there was multiple clocking wizard in the design, so there are no issue in the design.


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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