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Contributor
Contributor
3,512 Views
Registered: ‎09-20-2011

Multi clock domains with EDK import

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Hello,

 

I am trying to construct a design which incorporates multiple clock domains which are connected by shared memory and in addition to this I am also trying to import a EDK project which access other shared memories (not the same ones) thought the axi interface. 

 

I am able to successfully compile a multi clock domain project and a edk import project independently however when I try to combine them into one sysgen project, I always receive errors without any details.

 

Is what I am trying to achieve possible in the current version of sysgen?

 

Thank you,

Donny

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Adventurer
Adventurer
3,839 Views
Registered: ‎08-20-2007

Re: Multi clock domains with EDK import

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Just read the "Generating Multiple Cycle-True Islands for Distinct Clocks section of Sysgen Manual. There is a note:

"The Multiple Subsystem Generator block does not support designs that include an EDK Processor block"

So I assume, the answer from Xilinx is still - No.

View solution in original post

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Adventurer
Adventurer
3,507 Views
Registered: ‎08-20-2007

Re: Multi clock domains with EDK import

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I would expect the answer - No, because EDK Processor blocks searches automatically for all shared memories in the design and maps them to appropriate blocks in it's subsystem. It has no possibility to check if specific shared memory block already has it's "mirror" in other time-domain subsytem.

But perhaps I'm wrong...

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Contributor
Contributor
3,503 Views
Registered: ‎09-20-2011

Re: Multi clock domains with EDK import

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That is what i assumed at first, but when i tried it, i was proven wrong. The EDK processor block did not map the shared memories which had their pair already in the design. In other words, if there was an To_FIFO 'fifo_test' and a FROM_FIFO 'fifo_test' in the design, the EDK processor did not include 'fifo_test' in its list. The EDK block only includes shared memories which do not have pairs.

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Adventurer
Adventurer
3,840 Views
Registered: ‎08-20-2007

Re: Multi clock domains with EDK import

Jump to solution

Just read the "Generating Multiple Cycle-True Islands for Distinct Clocks section of Sysgen Manual. There is a note:

"The Multiple Subsystem Generator block does not support designs that include an EDK Processor block"

So I assume, the answer from Xilinx is still - No.

View solution in original post

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