04-26-2012 12:19 AM
I have an ML605 board with an FMC150 ADC/DAC which I would like to use in system generator. I am trying to sample a an analog sinewave (from a frequency synthesizer) and display it on simulink.
So far, I could make the interface and I can get "something" from the frequency synthesizer out of the ADC on simulink, however due to timing inaccuracy, it is very distorted, however after performing FFT on my received signal, I can see a peek at the frequency I selected form the synthesizer.
I am generating a sine wave (in the range of 600 KHz to 2 MHz) and using the ADC at 60.44 MSPS. I am using the FPGA at a frequency of 100MHz from the (J9,H9) differential clock port on the ML605.
To address this timing problem, I am trying to take the clock output of the ADC (from ports different from J9,H9). However, I still need the 100 MHz clock for the SPI interface to control the ADC (that was written and imported in a black box).
Is there anyway to do this? to have 2 clocks from 2 different ports ? ,
I defined a new custom board (for my non-memory mapped ports from/to the ADC) , however one can select only 2 pins ( 1 differential port) for the clock , and generate multiple clocks using the multiple system generator - but this has the limitation that the clocks shall be multiples of each other.
Any suggestions are welcome to address this issue.
04-26-2012 11:08 AM
I'm trying to do something like you. Actually I'm trying to control the FMC150 on the ML605 from the system generator. But I'm a bit lost. Could you give me any tips about how do you did the implementation of the interface to configure the ADC or could you attach your project?
Thank you very much.
04-27-2012 01:04 AM
Hi, Ahmed and Victor.
First of all, signal processing part should have same frequency as sampling frequency (or multiple of it). Is it possible to clock ADC with same clock as FPGA?
As far as I see FMC150 board has DSP Targeted Reference Design with ADC/DAC (RTL and Simulink):
Have you tried to get it?
04-27-2012 02:35 AM
"First of all, signal processing part should have same frequency as sampling frequency (or multiple of it)"
04-27-2012 07:16 AM
04-27-2012 07:48 AM
No I didn't try that. However I believe it wouldn't work , as the input frequency range from the FMC150 datasheet is
I tried signals @ 600KHz, 1MHz , 2 MHz... I then take the FIFO output, and i do the matlab FFT on it, I can get peaks close to those frequencies, they are distinguishable but inaccurate due to the timing issues I mentioned. and of course there are no peaks when I turn the RF off except at DC.
04-30-2012 09:34 AM
currently I could solve the distortion by taking the clock to the iDDR interface from the ADC clock. The iDDR was imported in a blackbox, which contains a DCM and iDELAY, I could map this port as a non-memory mapped port.
currently I have a minor clocking issue as I get glitch in the sinewave ... the sinewave is clear, but it has some glitches, due to the system running in a free running clock mode. so I made the shared fifo in sysgen, however, Its clock is taken from the sysclock of the board (which is 100 MHz) and the output rate of the ADC interface is 61.44 MHz.
Now my question is
How to let the shared fifo take the clock of the ADC (note that the clock of the ADC is a DDR clock, which is handled in the blackbox, which has an IDDR interface and mmcm) now I would like to take the clock output of this blackbox, and give it to the shared FIFO so as to tarnsfere my data without the glitches.
I think those glitches appear due to the DDR interface which is clocked by 61.44 MHz and the shared fifo is clocked by 100MHz ... so they are not multiples which results sometimes in loosing a bit from the DDR inputs from the ADC which results in this distortion.
Any suggestions or comments are welcome.