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Observer s_aelsok
Observer
6,554 Views
Registered: ‎03-19-2012

Multiple clocks in system generator

Hi all, 

 

I have an ML605 board with an FMC150 ADC/DAC which I would like to use in system generator. I am trying to sample a an analog sinewave (from a frequency synthesizer) and display it on simulink.

 

So far, I could make the interface and I can get "something" from the frequency synthesizer out of the ADC on simulink, however due to timing inaccuracy, it is very distorted, however after performing FFT on my received signal, I can see a peek at the frequency I selected form the synthesizer. 

 

I am generating a sine wave (in the range of 600 KHz to 2 MHz) and using the ADC at 60.44 MSPS. I am using the FPGA at a frequency of 100MHz from the (J9,H9) differential clock port on the ML605. 

 

To address this timing problem, I am trying to take the clock output of the ADC (from ports different from J9,H9). However, I still need the 100 MHz clock  for the SPI interface to control the ADC (that was written and imported in a black box). 

 

Is there anyway to do this? to have 2 clocks from 2 different ports ? ,

 

I defined a new custom board (for my non-memory mapped ports from/to the ADC) , however one can select only 2 pins ( 1 differential port) for the clock , and generate multiple clocks using the multiple system generator - but this has the limitation that the clocks shall be multiples of each other.

 

Any suggestions are welcome to address this issue.

 

Ahmed. 

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6 Replies
Visitor arabzaraq
Visitor
6,542 Views
Registered: ‎04-26-2012

Re: Multiple clocks in system generator

Hi Ahmed,

I'm trying to do something like you. Actually I'm trying to control the FMC150 on the ML605 from the system generator. But I'm a bit lost. Could you give me any tips about how do you did the implementation of the interface to configure the ADC or could you attach your project?

 

Thank you very much.

Victor.

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Explorer
Explorer
6,518 Views
Registered: ‎12-08-2010

Re: Multiple clocks in system generator

Hi, Ahmed and Victor.

 

First of all, signal processing part should have same frequency as sampling frequency (or multiple of it). Is it possible to clock ADC with same clock as FPGA?

 

As far as I see FMC150 board has DSP Targeted Reference Design with ADC/DAC (RTL and Simulink):

http://www.xilinx.com/products/boards-and-kits/AES-V6DSP-LX240T-G.htm

 

Have you tried to get it?

Best Regards,
Vitaly.
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Observer s_aelsok
Observer
6,513 Views
Registered: ‎03-19-2012

Re: Multiple clocks in system generator

Hi all, thank you both for your interest in my problem here, 
for Victor, 
what I did is that I investigated the getting started reference design, I modified it to fit into simulink. I removed the DDC, DUC and I removed the blocks specific to chipscope. I took the SPI interface to control the FMC150, the iDDR and IODELAY for interfacing with the data from the ADC, removed the loopback configuration , and took the input to the ADC directly from the frequency synthesizer. 
To do this, you have to define a new custom board form the system generator token, and then define the non-memory mapped ports ( ports that are on the board and not controlled in anyway by simulink - the control input/outputs for the FMC150) check the reference design for those , and then you have to define the  data input ports (the two channels from the ADC) as LVDS ports.
The limitation on this approach is the connection speed, you have to run the design in the free-running mode so as not to interrupt the sampling, and for interfacing I had to use a shared FIFO (64K depth), where the length of this FIFO is only the valid data, as it will get full at a certain point due to the speed difference between the ADC and the JTAG connection.
what I want is only the first 64K words in the FIFO , I just want to insure that my RF fronend can interface successfully with the virtex-6 DSP board.
for Vitaly,
The problem with the simulink reference design is that the FMC150 is not used ... the inputs are generated through an M-fie and then DDC , DUC are preformed on the FPGA. It even uses a single stepped clock. 

"First of all, signal processing part should have same frequency as sampling frequency (or multiple of it)"

and this is exactly my question :  
For the DSP part (namely the IDDR here as I haven''t added the rest of the DSP part yet ), I would like to take the clock from the ADC, and for the SPI(which configures the ADC) I would like to use the 100 MHz clock from the ML605. 
However you have only one choice for clocking and then the rest of the design shall have the clocks multiple of this one clock.
Thank you very much for your feedback, please tell me if you have further comments or suggestions.
Best regards,
Ahmed.
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Visitor arabzaraq
Visitor
6,501 Views
Registered: ‎04-26-2012

Re: Multiple clocks in system generator

Hi Ahmed,

Thanks for your help.
You tried to read a dc signal instead a sinusoid? It worked with the dc signal?

Best Regards,
Victor.
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Observer s_aelsok
Observer
6,494 Views
Registered: ‎03-19-2012

Re: Multiple clocks in system generator

Hi Victor, 

 

No I didn't try that. However I believe it wouldn't work , as the input frequency range from the FMC150 datasheet is

0.4-500 MHz.

 

I tried signals @ 600KHz, 1MHz , 2 MHz... I then take the FIFO output, and i do the matlab FFT on it, I can get peaks close to those frequencies, they are distinguishable but inaccurate due to the timing issues I mentioned.  and of course there are no peaks when I turn the RF off except at DC.

 

Best regards,

Ahmed.

 

 

 

 

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Highlighted
Observer s_aelsok
Observer
6,482 Views
Registered: ‎03-19-2012

Re: Multiple clocks in system generator

currently I could solve the distortion by taking the clock to the iDDR interface from the ADC clock. The iDDR was imported in a blackbox, which contains a DCM and iDELAY, I could map this port as a non-memory mapped port.

 

currently I have a minor clocking issue as I get glitch in the sinewave ... the sinewave is clear, but it has some glitches, due to the system running in a free running clock mode. so I made the shared fifo in sysgen, however, Its clock is taken from the sysclock of the board (which is 100 MHz) and the output rate of the ADC interface is 61.44 MHz.

 

Now my question is

How to let the shared fifo take the clock of the ADC (note that the clock of the ADC is a DDR clock, which is handled in the blackbox, which has an IDDR interface and mmcm) now I would like to take the clock output of this blackbox, and give it to the shared FIFO so as to tarnsfere my data without the glitches. 

 

I think those glitches appear due to the DDR interface which is clocked by 61.44 MHz and the shared fifo is clocked by 100MHz ... so they are not multiples which results sometimes in loosing a bit from the DDR inputs from the ADC which results in this distortion.

 

Thanks, 

Any suggestions or comments are welcome.

 

best regards, 

Ahmed.

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