01-10-2019 04:42 AM
Hi, We are trying to run the tricube applicatiion by following this tutorial :https://www.xilinx.com/support/documentation/sw_manuals/xilinx2016_4/ug1209-embedded-design-tutorial.pdf on ultrazed EG with the carrier board.
While building it is throwing assertion failed errors (Please refer the log file attached). We can run the application but there is no output on the display.
NOTE : The following command: /usr/bin/Xorg -depth 16& is changed to /usr/bin/Xorg -depth 24& since we are using DELL monitor.
01-11-2019 05:59 AM
Are you using a Displayport monitor (i.e. no DP to HDMI/VGA/DVI adapter)? If not please use a DP monitor.
If you do not have one, please make sure you are using an active adapter. Passive adapters are not supported by the DP controller.
01-21-2019 03:18 AM
01-21-2019 08:04 AM
What vivado/SDK/petalinux version are you using? Did you try with 2018.3
01-28-2019 05:31 AM
Did you try with any pre-built images for the ultrazed board? Are you able to get any output on the DP monitor at all?
02-06-2019 05:34 AM
Yes, But it is loading from emmc flash instead of memory card even though the dip switches are in correct position.
02-12-2019 01:58 AM
How do you know that it it is loading from the flash instead of the SD card?
05-16-2019 03:47 AM
The prebuilt image is working and I can see the tricube on the display. Now I used the ug1209 document to build the image from scratch. How ever I am still facing the issue (Nooutput on display)although log seems to be fine except the following lines:
1. /etc/X11/Xsession.d/90XWindowManager.sh: line 6: /usr/bin/x-window-manager: No such file or directory
xinit: conn[ 28.609096] PLL: shutdown
ection to X server lost
Attached the whole log for your reference.
Note: In vivado design I had changed the VPLL to be used only with DP VIDEO. From the ug1209 document I saw that the lane selection for the display port should be dual lower which when I try to change shows error as this is also used by sata and usb. So I disabled both SATA and usb. Please see the attached image for clock configuration.