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12-19-2018 05:29 AM
Hello,
I have tested HDMI in & out design in ZCU102 kit. Now I am targetting same in our custom ZU4EG device based SoM with TB-FMCH-HDMI4K FMC based HDM card. In the compilation I am getting error for TMDS clock out from Video PHY.
" [Vivado 12-1411] Cannot set LOC property of ports, Could not legally place terminal HDMI_TX_CLK_P_OUT at K12 (IOB_X0Y156) since it belongs to a shape containing instance exdes_i/vid_phy_controller/inst/gt_usrclk_source_inst/tx_mmcm.GT0_TX_MMCM_CLKOUT1_OBUFTDS_INST. The shape requires relative placement between HDMI_TX_CLK_P_OUT and exdes_i/vid_phy_controller/inst/gt_usrclk_source_inst/tx_mmcm.GT0_TX_MMCM_CLKOUT1_OBUFTDS_INST that can not be honoured because it would result in an invalid location for exdes_i/vid_phy_controller/inst/gt_usrclk_source_inst/tx_mmcm.GT0_TX_MMCM_CLKOUT1_OBUFTDS_INST. "
I compared the pin type against ZCU102. In ZCU102, the TMDS clock out is connected to GCLK pin where as in ZU4EG device is connected to User IO. I see OBUFTDS is driving the TMDS clock output from video phy controller.
Is there any constraint for TMDS clock output to connect to GC/QBC/DBC pins?
We have one more version of ZU7CG and custom carrier card where HDMI Out is tested. In this case the TMDS clock out is given to QBC pin. Also, in the ZU4EG case, the tool is assigning the pin to one of the available DBC pins.
Is there any constraint in any of generated xdc files of HDMI passthrough design to instruct the tool to look for GC/DBC/QBC pins for TMDS clock output?
With regards,
Hariprasad Bhat
12-21-2018 01:43 AM
Please take a look at TMDS Clock Section in Chapter 4 of PG230, the IOSTANDARD for HDMI_TX_CLK_P_OUT should be LVDS, which is true differential IOSTANDARD.
As per page 343-344 of UG571, I notice there are two limitation for the I/O in HD bank :
1. the max data rates is only up to 250Mb/s, which isn't enough for HDMI application
2. It only supports single-ended, or pseudo-differential standards, like DIFF_SSTL15, as output standard. The true differential IOSTANDARD is only supported as input, not output.
That's why you can't use the IOs from HD bank
12-20-2018 06:33 AM
Hello @hariprasadb,
Can your share the xdc file and the exact part you are using?This way we can try to reproduce and investigate
I assume you are using the example design without modification (except the pin location and the part?)
Thanks,
12-20-2018 06:49 AM
Hi @florentw,
Attached the xdc file.
Yes, example design without modification (except the pin location and the part (xczu4eg-fbvb900-1-e)).
Further, we continued debugging by assigning some other user IOs (not K12 as in xdc). With that compilation is passing. Looks like problem with the IOB_X0Y156. Need to analyze the root cause.
With Regards,
Hariprasad Bhat
12-20-2018 11:27 PM
Hi @florentw
I checked further and noticed below similarity.
Could this be a issue for the placement failure?
Also, one link gives some insight on HIGH_DENSITY bank usage.
With Regards,
Hariprasad Bhat
12-21-2018 01:43 AM
Please take a look at TMDS Clock Section in Chapter 4 of PG230, the IOSTANDARD for HDMI_TX_CLK_P_OUT should be LVDS, which is true differential IOSTANDARD.
As per page 343-344 of UG571, I notice there are two limitation for the I/O in HD bank :
1. the max data rates is only up to 250Mb/s, which isn't enough for HDMI application
2. It only supports single-ended, or pseudo-differential standards, like DIFF_SSTL15, as output standard. The true differential IOSTANDARD is only supported as input, not output.
That's why you can't use the IOs from HD bank