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Adventurer
Adventurer
642 Views
Registered: ‎08-16-2017

Potential mismatch between documentation and example of CSI-RX IP core in 2018.3

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Vivado 2018.3:

I am using the v4.0 of the CSI-RX IP core, the documentation PG232 states that output video data, in case of 2 ppc, is MSB justified. However, the example design uses a subset converter (the one driving the demosaicing) and seems to map the RAW10 to RAW8 using :

tdata[19:12],tdata[9:2]

which indicates that the RAW10 data was "LSB" justified as was the case with previous versions. While I expected to see :

tdata[23:16],tdata[11:4]

according to

could anyone confirm this? 

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Moderator
Moderator
562 Views
Registered: ‎11-09-2015

Re: Potential mismatch between documentation and example of CSI-RX IP core in 2018.3

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Hi @ziladdev,

This all depends on how the maximum is set.

In the pg232, you are set for max RAW12, so your boundary will be aligned on 12-bits. Then, if on the same interface you are doing a lower bpc, then the data will be MSB aligned inside the component

Thus RAW10 transfered over a max RAW12 interface is sent as

Component 1: [11:2] Component 2: [23:14].

But RAW10 transfered over a max RAW10 interface is sent as

Component 1: [9:0] Component 2: [19:10].

Hope that clarifies


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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6 Replies
Moderator
Moderator
618 Views
Registered: ‎11-09-2015

Re: Potential mismatch between documentation and example of CSI-RX IP core in 2018.3

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Hi @ziladdev,

You need to be careful about the MSB alignment. This is aligned inside a "component". This means that you have to take in account the highest bpc configuration. This will give you the boundary of your component. The component are LSB aligned.

Then inside the component, the data will be MSB aligned.

So let say you are configured in 10 bit per component with 2 pixel per clock so you would be

Component 1: [9:0] - Component 2: [19:10].

Note that you would need the width of the AXI interface to be 20bit. But because the AXI4 spec requires to be a number of byte then you would add padding data and get the width to 24-bits (3byte)

Then if you want to do 8 bpc on the same interface, you would align the data inside a component which give you

Component 1: [19:12] - Component 2: [9:2]

This looks correct to me.


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Xilinx Employee
Xilinx Employee
602 Views
Registered: ‎03-30-2016

Re: Potential mismatch between documentation and example of CSI-RX IP core in 2018.3

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Hello @ziladdev

Generated and check the Example design from 2018.3/2018.1 ,  the bit assignment is correct as mentioned by @florentw. MIPI CSI-2 RX outputs 10bits video data, but only [9:2] part is used because the rest of the modules are designed to work at 8 bit.


Thanks & regards
Leo

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Adventurer
Adventurer
577 Views
Registered: ‎08-16-2017

Re: Potential mismatch between documentation and example of CSI-RX IP core in 2018.3

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So let say you are configured in 10 bit per component with 2 pixel per clock so you would be

Component 1: [9:0] - Component 2: [19:10].

 


Please, explain then why according to PG232 v4, page 10,  Example 1 (December 5, 2018).

RAW 8 is stored as

Component 1: [11:4] Component 2: [23:16].

From that it seems natural that RAW 10 will be :

Component 1: [11:2] Component 2: [23:14].

This is very confusing....

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Moderator
Moderator
563 Views
Registered: ‎11-09-2015

Re: Potential mismatch between documentation and example of CSI-RX IP core in 2018.3

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Hi @ziladdev,

This all depends on how the maximum is set.

In the pg232, you are set for max RAW12, so your boundary will be aligned on 12-bits. Then, if on the same interface you are doing a lower bpc, then the data will be MSB aligned inside the component

Thus RAW10 transfered over a max RAW12 interface is sent as

Component 1: [11:2] Component 2: [23:14].

But RAW10 transfered over a max RAW10 interface is sent as

Component 1: [9:0] Component 2: [19:10].

Hope that clarifies


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
Adventurer
Adventurer
556 Views
Registered: ‎08-16-2017

Re: Potential mismatch between documentation and example of CSI-RX IP core in 2018.3

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I think I got it, I somewhat thought the maximum is set corresponding to how wide the actual AXIS, i.e. byte aligned interface, is.
With 10bits, the width is 24bits (2ppc x10 =20 ...+1 nibble to make it byte aligned) and that the bounday was automatically set to half of 24 = 12 bits. The tables did somewhat reinforce this while referring to mixed ppc interfaces.

So RAW10, transported over a max RAW10 interface still maintains its bounday at the 10th bit and not the 12th.
Xilinx Employee
Xilinx Employee
542 Views
Registered: ‎03-30-2016

Re: Potential mismatch between documentation and example of CSI-RX IP core in 2018.3

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Hello @ziladdev

I believe your questions are already answeted by @florentw.
If everything is clear, please kindly mark his response as solution (click on "Accept as solution" button below the reply) , so others can learn from your experience.

Thanks and regards
Leo

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