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Visitor muneet
Visitor
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Registered: ‎06-18-2018

Problem with Video Connectivity Display Port Rx/Tx Subsystem IP core customisation in 2018.1

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Hi,

I am using Kintex-7 FPGA and there is a warning "IP 'DisplayPORT RX Subsystem' can be used within IP Integrator only". I want to recustomise it and then use it. WIth other IPs of Video Connectivity like MIPI Subsytem or HDMI Subsystem, there is no problem. Kindly suggest a way how can I use this DisplayPort Subsystem by customising it as per the requirement. The screenshot is attached for the sameDP_IP problem.JPG

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Moderator
Moderator
618 Views
Registered: ‎10-04-2017

Re: Problem with Video Connectivity Display Port Rx/Tx Subsystem IP core customisation in 2018.1

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Hi @muneet,

 

As the warning states, this IP is only intended to be used within an IPI system. Because of this, to customize or re-customize the IP you will have to do so within IPI.

 

 

The easiest way to to do this is to create a block design and only have the DisplayPort core in the design. To do this:

1. Create a new IPI Block Design.

2. Add the DisplayPort IP and customize it for your needs.

3. Right click on the IP and select "make external." This will push all IO from the IP outside of the block design.

4. You can now instantiate the Block Design in your RTL code.

 

*There are other ways to accomplish this but this is the easiest and my suggestion is to use IPI for your Video projects. For most use-cases, IPI increases productivity.

 

Regards,

Sam

 

Don't forget to reply, kudo, and accept as solution.

Xilinx Video Design Hub

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2 Replies
Moderator
Moderator
619 Views
Registered: ‎10-04-2017

Re: Problem with Video Connectivity Display Port Rx/Tx Subsystem IP core customisation in 2018.1

Jump to solution

Hi @muneet,

 

As the warning states, this IP is only intended to be used within an IPI system. Because of this, to customize or re-customize the IP you will have to do so within IPI.

 

 

The easiest way to to do this is to create a block design and only have the DisplayPort core in the design. To do this:

1. Create a new IPI Block Design.

2. Add the DisplayPort IP and customize it for your needs.

3. Right click on the IP and select "make external." This will push all IO from the IP outside of the block design.

4. You can now instantiate the Block Design in your RTL code.

 

*There are other ways to accomplish this but this is the easiest and my suggestion is to use IPI for your Video projects. For most use-cases, IPI increases productivity.

 

Regards,

Sam

 

Don't forget to reply, kudo, and accept as solution.

Xilinx Video Design Hub

View solution in original post

Moderator
Moderator
553 Views
Registered: ‎11-09-2015

Re: Problem with Video Connectivity Display Port Rx/Tx Subsystem IP core customisation in 2018.1

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Hi @muneet,

Was @samk's reply enough for you?

If your question is answered or your issue is solved, please kindly mark the response which helped as solution (click on "Accept as solution" button below the reply)

If this is not solved/answered, please reply in the topic giving more information on your current status.

Thanks and Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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