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Observer gusichen
Observer
5,950 Views
Registered: ‎10-21-2007

Problems about Link for Modelsim

hi experts. i'm not sure whether it is polited to ask this question here.if you could't answer my question,could you please tell me where to ask them,thanks.my question is below.
how to mapping the sample clock in MATLAB to the main clock in HDL module?in MATLAB function, tnext = tnow+x. 'x' means the time space when MATLAB callback data from Modelsim.but i don't know how to specify the time space when Modelsim call MATLAB's signal,for example,i wrote a testbench in MATLAB.
thanks.
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Xilinx Employee
Xilinx Employee
5,939 Views
Registered: ‎08-07-2007

Re: Problems about Link for Modelsim

If you're using a System Generator HDL Black Box then the clock rate of the HDL is determined by two factors.  First the Simulink System Period set in the System Generator token.  Next the sample rate of the HDL block itself relative to the System Generator token.  If these are both 1 then the clock which drives your HDL module will have a 1 second period. 

If you'd like this to be a more representative time of your actual system then you can decrease the Simulink System Period in the token as desired and be sure to change gateways and other rate determining blocks to match appropriately.  Keep in mind that if you do this then your simulation run time and the simulink sources sample periods (where appropriate) should also be decreased to match the new scale.

However, all this is not necessary if you are only doing a behavioral simulation where the timing is not relavent, only the ratios are important in how they relate to your actual system clock period.

For further details see the sections titled "Hardware design using System Generator > System Level Modeling" and "Hardware design using System Generator > Automatic code generation" in the System Generator User Guide.
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