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Contributor
Contributor
4,229 Views
Registered: ‎08-21-2009

Problems using dsp48 / timing constraint failed

Hi all!

At the moment I'm facing the following problem.

I created an IP-template with CIP, than I wrote

an FIR-Filter in VHDL. If I try to implement the design

an timing error occurs.

With the help of ISE timing analysis I found out that

there is to much logic in one path.

The biggest delay occurs between the dsp48-cores

on Signal PCIN / PCOUT.

My VHDL design is like the following:

 

 

MUL_ADD: process(Bus2IP_Clk, Bus2IP_Reset) variable PRODUCTS : PRODUCTS_TYPE; variable ADD : signed(0 to 23); begin if Bus2IP_Reset = '1' then ADDA_delay <= (others => '0'); elsif Bus2IP_Clk = '1' and Bus2IP_Clk'event then MUL: for I in 0 to TAPS loop if I <= (TAPS/2) then PRODUCTS(I) := STAGE(I) * COEFF(I); else PRODUCTS(I) := STAGE(I) * COEFF(TAPS-I); end if; end loop; ADD := PRODUCTS(0)(0 to 23); AKKU: for I in 1 to TAPS loop ADD := ADD + PRODUCTS(I); end loop; ADDA_delay <= ADD; end if; end process MUL_ADD;

Due to that I use the DSP48 indirect because I do not instance it I do not really know

how to solve the problem. Is there a way to put some "delay FlipFlops" between

PCIN / PCOUT without instance the DSP48 directly?

I would appreciate if anyone could help me with this issue!

 

Regards Chris

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2 Replies
Xilinx Employee
Xilinx Employee
4,200 Views
Registered: ‎11-28-2007

Re: Problems using dsp48 / timing constraint failed

If I understand you code correctly, you're creating a big adder chain without any pipeline register after each tap. I would suggest you rewrite the adder chain code so that a pipeline register is added after addition of each product (see attached snapshot is an example with cascaded adders for Virtex6).

 


c.schmidt wrote:

ADD := PRODUCTS(0)(0 to 23);
AKKU: for I in 1 to TAPS loop
ADD := ADD + PRODUCTS(I);

end loop;

Cheers,
Jim
ScreenHunter_03 Jan. 09 14.21.gif
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Contributor
Contributor
4,190 Views
Registered: ‎08-21-2009

Re: Problems using dsp48 / timing constraint failed

Hi Jimwu!

 

Thanks for your reply!

In the meantime I got same answer from my local Xilinx FAE.

 

Regards

 

Chris

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