UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Adventurer
Adventurer
2,288 Views
Registered: ‎09-18-2017

Problems with VDMA (VTPG,VDMA,MIG7,DDR3)

Jump to solution

Hello!

Currently, I have been working on getting my design. It went well at the beginning and I literally thought my VDMA code was working until I started simulating it and then saw that there were some problems. I am trying to configure a whole system that takes a random picture and saves it into the DDR3 SDRAM which in other includes peripherals like VTPG,VDMA,uB and MIG7.

So the data flow is:

  1. uB -> gives instruction to the peripherals by writing to the registers.
  2. VTPG-> configured to stream a (24bit) picture
  3. VDMA -> configured to save the picture into the DDR3 going through the MIG7.

 

Firstly, what I did was to set up the VTPG (Test Pattern Generator) by using the provided APIs and it worked well with an HDMI screen. So, I have confirmed that video Streaming works since no addresses are needed. However, when I check the path from S2MM OR MM2S I encounter problems which are illustrated below. All related files are attached which gives more info. 

 

PROBLEM1

application VDMA AND VTPG STOPS.png

As you see from the picture, my VDMA peripheral and VTPG peripheral stops working ( block design is attached). So I am just going through 5 addresses and then it stops totally. Moreover, after a certain amount of time, the VTPG stops generating data as well. 

 

PROBLEM2

VDMA STOPS.png

 This picture gives a clearer view of what is happening with the VDMA signal. 

 

PROBLEM 3

 

VTPG STOPS.png

As you see, the VTPH stops working after 93 samples.

 

settings for peripherals.png

 

This is my peripheral settings.

 

 

 

Address editor.png

This is my address settings

 

In my linker script, all the information is mapped to the BRAM and not the main memory (DD33).

Further, I got the same issue when I was running the triple-buffering example thus making my application to fail.

 

Here is my code. I can briefly explain what I did. I set the important register to make the VDMA work and also use the API to initialize the VTPG. 

 

/************************************************************************/
/* */
/* video_demo.c -- Nexys Video HDMI demonstration */
/* */
/************************************************************************/
/* Author: Sam Bobrowicz */
/* Copyright 2015, Digilent Inc. */
/************************************************************************/
/* Module Description: */
/* */
/* This file contains code for running a demonstration of the */
/* Video input and output capabilities on the Nexys Video. It is a good */
/* example of how to properly use the display_ctrl and */
/* video_capture drivers. */
/* */
/* */
/************************************************************************/
/* Revision History: */
/* */
/* 11/25/2015(SamB): Created */
/* 03/31/2017(ArtVVB): Updated sleep functions for 2016.4 */
/* */
/************************************************************************/

/* ------------------------------------------------------------ */
/* Include File Definitions */
/* ------------------------------------------------------------ */

#include "platform.h"
#include <stdio.h>
#include "xil_io.h"
#include "xv_tpg.h"
#include "xgpio.h"
#include "xvidc.h"
#include "xaxivdma.h"
//#include "xuartps.h"
#include "math.h"
#include <ctype.h>
#include <stdlib.h>
#include <xil_cache.h>

#include "xparameters.h"



/*
* XPAR redefines
*/
#define VGA_VDMA_ID XPAR_AXIVDMA_0_DEVICE_ID
#define SCU_TIMER_ID XPAR_AXI_TIMER_0_DEVICE_ID
#define UART_BASEADDR XPAR_UARTLITE_0_BASEADDR
#define VTPG_ID XPAR_V_TPG_0_DEVICE_ID
#define DDR3_MIG_STARTADDRESS XPAR_MIG_7SERIES_0_BASEADDR
#define GPIO_1_DEVICE_ID XPAR_GPIO_1_DEVICE_ID
#define NUM_TEST_MODES (2)

/* ------------------------------------------------------------ */
/* Global Variables */
/* ------------------------------------------------------------ */

/*
* Display and Video Driver structs
*/

XGpio Gpio; /* The Instance of the GPIO Driver */

XV_tpg Tpg;
XV_tpg_Config *Tpg_ConfigPtr;
XTpg_PatternId Pattern; /**< Video pattern */


/*registers for VDMA*/
#define PARK_PTR_REG 0x28
#define VDMA_VERSION 0x2C
#define S2MM_FRMDLY_STRIDE 0xa8
#define MM2S_FRMDLY_STRIDE 0x58

/*S2MM registers*/
#define S2MM_VDMACR 0x30
#define S2MM_VDMASR 0x34
#define S2MM_VDMA_IRQ_MASK 0x3C
#define S2MM_REG_INDEX 0x44

#define S2MM_VSIZE 0xa0
#define S2MM_HSIZE 0xa4

#define S2MM_START_ADDRESS1 0xac
#define S2MM_START_ADDRESS2 0xb0
#define S2MM_START_ADDRESS3 0xb4

/*MM2S registers*/
#define MM2S_VDMACR 0x00 // This register provides control for the Memory Map to Stream VDMA Channel.
#define MM2S_VDMASR 0x04 //
#define MM2S_REG_INDEX 0x14

#define MM2S_FRMDLY_STRIDE 0x58
#define MM2S_VSIZE 0x50
#define MM2S_HSIZE 0x54

#define MM2S_START_ADDRESS1 0x5C
#define MM2S_START_ADDRESS2 0x60
#define MM2S_START_ADDRESS3 0x64


/* ------------------------------------------------------------ */
/* Procedure Definitions */
/* ------------------------------------------------------------ */

static void ConfigTpg(XVidC_VideoStream *StreamPtr);


/*** Global Variables ***/
unsigned int srcBuffer = DDR3_MIG_STARTADDRESS + 0x01000000;
unsigned int vdmaBaseAddr = XPAR_AXI_VDMA_0_BASEADDR;



int main()
{
init_platform();
XAxiVdma InstancePtr;
unsigned int vdmaRegisterData = 0;
unsigned int vdmaRegisterAddr = 0;
int Status;

/*Configure the MM2S channels and operation*/
vdmaRegisterData = 0x0000808B; // starts the DMA and configures settings regarding the MM2S channels
vdmaRegisterAddr = MM2S_VDMACR;//This register provides control for the Memory Map to Stream VDMA Channel.
vdmaSet(vdmaBaseAddr,vdmaRegisterAddr,vdmaRegisterData);
vdmaRegisterData = 0x0000808B; // starts the DMA and configures settings regarding the MM2S channels
vdmaRegisterAddr = S2MM_VDMACR;//This register provides control for the Memory Map to Stream VDMA Channel.
vdmaSet(vdmaBaseAddr,vdmaRegisterAddr,vdmaRegisterData);

vdmaRegisterData = 0x00000280; //(stride setting) select the number of adresss bytes between every first pixel line
vdmaRegisterAddr = MM2S_FRMDLY_STRIDE;
vdmaSet(vdmaBaseAddr,vdmaRegisterAddr,vdmaRegisterData);

vdmaRegisterData = 0x00000780; // Horizontal size 640*3 => 1920
vdmaRegisterAddr = MM2S_HSIZE;
vdmaSet(vdmaBaseAddr,vdmaRegisterAddr,vdmaRegisterData);

vdmaRegisterData = 0x000001E0; // vertical size 480
vdmaRegisterAddr = MM2S_VSIZE;
vdmaSet(vdmaBaseAddr,vdmaRegisterAddr,vdmaRegisterData);

vdmaRegisterData = srcBuffer; // Frame start address for the first frame ( x frames need x start addresses in this case we use 1 frame).
vdmaRegisterAddr = MM2S_START_ADDRESS1; // we use one frame buffer and want to read from memory and put it into stream application
vdmaSet(vdmaBaseAddr,vdmaRegisterAddr,vdmaRegisterData);

vdmaRegisterData = srcBuffer + 0x0f000000; // Frame start address for the first frame ( x frames need x start addresses in this case we use 1 frame).
vdmaRegisterAddr = MM2S_START_ADDRESS2; // we use one frame buffer and want to read from memory and put it into stream application
vdmaSet(vdmaBaseAddr,vdmaRegisterAddr,vdmaRegisterData);

vdmaRegisterData = srcBuffer + 0x10000000; // Frame start address for the first frame ( x frames need x start addresses in this case we use 1 frame).
vdmaRegisterAddr = MM2S_START_ADDRESS3; // we use one frame buffer and want to read from memory and put it into stream application
vdmaSet(vdmaBaseAddr,vdmaRegisterAddr,vdmaRegisterData);


vdmaRegisterData = 0x00000280; //(stride setting) select the number of adress bytes between every first pixel line
vdmaRegisterAddr = S2MM_FRMDLY_STRIDE;
vdmaSet(vdmaBaseAddr,vdmaRegisterAddr,vdmaRegisterData);

vdmaRegisterData = 0x00000780; // Horizontal size 640*3 => 1920
vdmaRegisterAddr = S2MM_HSIZE;
vdmaSet(vdmaBaseAddr,vdmaRegisterAddr,vdmaRegisterData);

vdmaRegisterData = 0x000001E0; // vertical size 480
vdmaRegisterAddr = S2MM_VSIZE;
vdmaSet(vdmaBaseAddr,vdmaRegisterAddr,vdmaRegisterData);

vdmaRegisterData = srcBuffer; // Frame start address for the first frame ( x frames need x start addresses in this case we use 1 frame).
vdmaRegisterAddr = S2MM_START_ADDRESS1; // we use one frame buffer and want to read from memory and put it into stream application
vdmaSet(vdmaBaseAddr,vdmaRegisterAddr,vdmaRegisterData);

vdmaRegisterData = srcBuffer + 0x0f000000; // Frame start address for the first frame ( x frames need x start addresses in this case we use 1 frame).
vdmaRegisterAddr = S2MM_START_ADDRESS2; // we use one frame buffer and want to read from memory and put it into stream application
vdmaSet(vdmaBaseAddr,vdmaRegisterAddr,vdmaRegisterData);
vdmaRegisterData = srcBuffer + 0x10000000; // Frame start address for the first frame ( x frames need x start addresses in this case we use 1 frame).

vdmaRegisterAddr = S2MM_START_ADDRESS3; // we use one frame buffer and want to read from memory and put it into stream application
vdmaSet(vdmaBaseAddr,vdmaRegisterAddr,vdmaRegisterData);

DemoInitialize();
XGpio_DiscreteWrite(&Gpio, 1, 0b11);

while(1);


cleanup_platform();
return 0;
}

void XV_ConfigTpg(XV_tpg *InstancePtr) {
XV_tpg *pTpg = InstancePtr;
u32 width, height;
width = 640;
height = 480;
Pattern = XTPG_BKGND_COLOR_BARS;
/* Stop TPG */
XV_tpg_DisableAutoRestart(pTpg);
XV_tpg_Set_height(pTpg, height);
XV_tpg_Set_width(pTpg, width);
XV_tpg_Set_colorFormat(pTpg, XVIDC_CSF_RGB);
XV_tpg_Set_bckgndId(pTpg, Pattern);
XV_tpg_Set_ovrlayId(pTpg, 0);
XV_tpg_Set_enableInput(pTpg, 1);

XV_tpg_Set_passthruStartX(pTpg, 0);
XV_tpg_Set_passthruStartY(pTpg, 0);

XV_tpg_Set_passthruEndX(pTpg, width);
XV_tpg_Set_passthruEndY(pTpg, height);

/* Start TPG */
XV_tpg_EnableAutoRestart(pTpg);
XV_tpg_Start(pTpg);
}


void DemoInitialize()
{
int Status;

/* Initialize the GPIO driver */
Status = XGpio_Initialize(&Gpio, GPIO_1_DEVICE_ID);
if (Status != XST_SUCCESS) {
xil_printf("Gpio Initialization Failed\r\n");
return XST_FAILURE;
}
/* Set the direction for all signals as inputs except the LED output */
XGpio_SetDataDirection(&Gpio, 1, 0x0);
/*
* Initialize the Display controller and start it
*/

Tpg_ConfigPtr = XV_tpg_LookupConfig(VTPG_ID);


if (Tpg_ConfigPtr == NULL) {
Tpg.IsReady = 0;
return (XST_DEVICE_NOT_FOUND);
}

Status = XV_tpg_CfgInitialize(&Tpg, Tpg_ConfigPtr,
Tpg_ConfigPtr->BaseAddress);
if (Status != XST_SUCCESS) {
xil_printf("ERR:: TPG Initialization failed %d\r\n", Status);
return (XST_FAILURE);
}

XV_ConfigTpg(&Tpg);


return;
}


int vdmaSet(int vdmaBaseAddress, int registerAddress, int dataValue){
int VDMA_RegAddr = vdmaBaseAddress + registerAddress;
Xil_Out32(VDMA_RegAddr,dataValue);
}

void vdmaGet(int vdmaBaseAddress, int registerAddress){
int VDMA_RegAddr = vdmaBaseAddress + registerAddress;
int currentRegisterValue;
currentRegisterValue = Xil_In32(VDMA_RegAddr);
xil_printf("The register value is %x\r\n", currentRegisterValue);
}

 

So to sum it up, either I am not configuring the VDMA correctly or I have maybe missed a small step. I would be very glad if you could help me with this issue. If there is something that is unclear or misunderstanding please tell me. I have no interrupt or anything and want the VDMA to run freely.

 

 

The datasheet I am using for VDMA is 

https://www.xilinx.com/support/documentation/ip_documentation/axi_vdma/v6_2/pg020_axi_vdma.pdf.

 

I am attaching the block design below.

 

 

 

0 Kudos
1 Solution

Accepted Solutions
Moderator
Moderator
2,485 Views
Registered: ‎11-09-2015

Re: Problems with VDMA (VTPG,VDMA,MIG7,DDR3)

Jump to solution

Hi @azurath,

 

If everything is clear for you on this subject, please kindly mark a reply as solution to close the topic. Else please reply to the topic

 

Thanks and Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
0 Kudos
13 Replies
Moderator
Moderator
2,233 Views
Registered: ‎11-09-2015

Re: Problems with VDMA (VTPG,VDMA,MIG7,DDR3)

Jump to solution

Hi @azurath,

 

The VDMA has a status register. You might want to check if there are any. This would be the first thing I check in this case.

 

Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
0 Kudos
Adventurer
Adventurer
2,221 Views
Registered: ‎09-18-2017

Re: Problems with VDMA (VTPG,VDMA,MIG7,DDR3)

Jump to solution

Okay, yeah I will check in. Prior to checking the hardware, I was just using simulation. I'll ping you soon with more information regarding the problem.  

 

0 Kudos
Moderator
Moderator
2,196 Views
Registered: ‎11-09-2015

Re: Problems with VDMA (VTPG,VDMA,MIG7,DDR3)

Jump to solution

Hi @azurath,

 

Do you have any updates on this?

 

Thanks,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
0 Kudos
Adventurer
Adventurer
2,186 Views
Registered: ‎09-18-2017

Re: Problems with VDMA (VTPG,VDMA,MIG7,DDR3)

Jump to solution

Hello @florentw!

 

I have been debugging my design and did some changes which can be seen in my files that are attached. I have the WCFG file from the simulation and also a new block design ( added a smartAxi Connect). However, I am getting a very strange behavior which can be seen from the simulation file. Additionally, I have also checked my uB and  respective status register for the S2MM AND MM2S which showed to work, meaning "00011000" (hex bit 16 and 12 is high i.e no error flags are up): 

 

My simulation runs for 200uS where I am just manually controlling the Reset and the sys_clock_i pin in my design.

 

/*register address in my code */

# define S2MM_VDMASR 0x34
# define MM2S_VDMASR 0x04

 

Further, the Init_Calib_complete from the mig7 controller is not asserting while I am writing or reading from the DDR3. Could this be a problem during simulation? 

 

Another speculative bug can be the FIFO settings for each axi interconnects. I am suspicious that I am getting a FIFO buffer overflow because right now I can see 9 address transactions compared to before ( and this was achieved using the smart AXi interconnect).

 

However, the data and the address on the m_S2MM_axis on the simulation is not synchronized so there is a problem there. 

 

I am uploading the WCFG file from the simulation and also the new block design I have for my design.

 

PLUS

 

If you cannot open or see my simulation results in the WCFG tell me because then I have to upload pictures. 

0 Kudos
Adventurer
Adventurer
2,181 Views
Registered: ‎09-18-2017

Re: Problems with VDMA (VTPG,VDMA,MIG7,DDR3)

Jump to solution

DDR3.png

This is how the DDR3 work during 200uS as you see the init_calib_compelte is not going high and there is no write nor read transaction.

 

 

VDMA AND TPG.png

 

This shows my VDMA AND VTGP under 200uS

 

vdma and TPG ZOOMED.png

 

0 Kudos
Adventurer
Adventurer
2,177 Views
Registered: ‎09-18-2017

Re: Problems with VDMA (VTPG,VDMA,MIG7,DDR3)

Jump to solution

@florentw

Can it be that my register settings for the VDMA are incorrect  or that I do it in incorrect order?? 

 

 

Register values

MM2S_VDMACR 0x0000808B S2MM_VDMACR 0x0000808B MM2S_START_ADDRESS1 0x80000000U S2MM_START_ADDRESS1 0x80000000U MM2S_FRMDLY_STRIDE 0x00000280 MM2S_FRMDLY_STRIDE 0x00000280 MM2S_HSIZE 0x00000780 S2MM_HSIZE 0x00000780 MM2S_VSIZE 0x000001E0 S2MM_VSIZE 0x000001E0

 

 

0 Kudos
Adventurer
Adventurer
2,171 Views
Registered: ‎09-18-2017

Re: Problems with VDMA (VTPG,VDMA,MIG7,DDR3)

Jump to solution

@florentw

 

Did some changes please read now.

 

This is the register values printed on the Console when I run the uB processor and I am using the following function for that.

 

void vdmaGet(int vdmaBaseAddress, int registerAddress){
	int VDMA_RegAddr = vdmaBaseAddress + registerAddress;
	int currentRegisterValue =0;
	currentRegisterValue = Xil_In32(VDMA_RegAddr);
	xil_printf("The register value is %08x\r\n", currentRegisterValue);
}

 

The first register value is the  MM2S_VDMASR register and the second register value is the S2MM_VDMASR.

 

Console output

The register value is 00010000
The register value is 00010000
seconds 1
The register value is 00011000
The register value is 00011000
seconds 2
The register value is 00011000
The register value is 00011000
seconds 3
The register value is 00011000
The register value is 00011000
seconds 4
The register value is 00011000
The register value is 00011000
seconds 5
The register value is 00011000
The register value is 00011000

0 Kudos
Moderator
Moderator
2,161 Views
Registered: ‎11-09-2015

Re: Problems with VDMA (VTPG,VDMA,MIG7,DDR3)

Jump to solution

Hi @azurath,

 

Do you have the init_calib done high when you start sending data? For all your screenshot, you say that it is under 200us so I understand that the calibration is not done for the DDR...

 

Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
0 Kudos
Adventurer
Adventurer
2,159 Views
Registered: ‎09-18-2017

Re: Problems with VDMA (VTPG,VDMA,MIG7,DDR3)

Jump to solution

 @florentw

No, I don't actually know when it is supposed to go high? Is there any duration for that ?.. init_calib has always remained low under my simulations.

 

But there is a comment in the TCL console which is : 

 

PHY_INIT: Memory Initialization completed at          10405100000

 

is this pS? 

 

Further, if there is a time where I have to wait for the init_calib pin?

Can I somehow reduce that time? 

0 Kudos
Moderator
Moderator
1,409 Views
Registered: ‎11-09-2015

Re: Problems with VDMA (VTPG,VDMA,MIG7,DDR3)

Jump to solution

Hi @azurath,

 

I don't know... MIG is not my expertise...

However, in that case, I am just saying that I am not sure if you can expect a correct behaviour with the DDR if the calibration is not done...

 

You might want to use a VIP or a BRAM instead of the MIG for your simulation. It might help to ease things.

 

Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
0 Kudos
Adventurer
Adventurer
1,380 Views
Registered: ‎09-18-2017

Re: Problems with VDMA (VTPG,VDMA,MIG7,DDR3)

Jump to solution

 @florentw

 

Okay, I tested my design using an ILA, attached it to the init_calibration_complete pin and it was actually going high which confirms that the ddr3 actually work. I have also checked the memory using the TCF debugger and saw some values inside the ddr3 memory. My boss wants me to do it on a ddr3 so I don't know if the other peripherals are helpful. Do you have other colleagues that can take a look at this problem?

init_calib_complete goes high in hardware.png

0 Kudos
Moderator
Moderator
1,373 Views
Registered: ‎11-09-2015

Re: Problems with VDMA (VTPG,VDMA,MIG7,DDR3)

Jump to solution

Hi @azurath,

 

You started in simulation and now your in HW... For the init_calib done I was asking in simulation... Do not mix things

 

Do you have the same behaviour on the S2MM interface in HW as you have in simulation?


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
0 Kudos
Moderator
Moderator
2,486 Views
Registered: ‎11-09-2015

Re: Problems with VDMA (VTPG,VDMA,MIG7,DDR3)

Jump to solution

Hi @azurath,

 

If everything is clear for you on this subject, please kindly mark a reply as solution to close the topic. Else please reply to the topic

 

Thanks and Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
0 Kudos